UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer

The flexibility of RISC-V is the verification effort that must be devoted to all variants of the RISC-V cores.Considering the possible number of RISC-V core variants, it is not practical to manually implement and maintain all corresponding RTL representations and UVM environments. Automation is advisable, but it depends upon the configuration variability of RISC-V cores. The [...]

2018-08-24T05:25:31+00:0024th August, 2018|Blog, Thought Leadership|

A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs

A RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration.A RISC-V microprocessor can be configured in several architectural modes depending upon the target market and applications. Further, each microprocessor implementation can have different micro-architectural parameters depending upon performance, and power considerations. Arun Chandra & Dr. Mike Bartley [...]

2018-03-13T07:24:16+00:0013th March, 2018|Blog, Thought Leadership|

RISC-V Gains Its Footing

The RISC-V instruction-set architecture, which started as a UC Berkeley project to improve energy efficiency, is gaining steam across the industry.While it’s simple to view RISC-V in terms of what is already available in the market today, the architecture opens new options in markets that are either still immature, or which are just starting to [...]

2018-03-07T07:09:53+00:007th March, 2018|Blog, Thought Leadership|