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How Much Verification Is Necessary?

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. This article from Semiengineering highlights how much verification needs to be done, when to do it, and how to do [...]

The Secret To Reaching Rapid Verification Closure

This article from Semiengineering describes how to reduce RTL verification time in order to meet aggressive schedules with increased functionality & more productivity and describes how to achieve 100% RTL Functional and Code Coverage. Read More Find out how T&VS has enabled clients to improve the quality of their outgoing IP through advanced verification techniques.