Tag Archives: RTL Verification

How Much Verification Is Necessary?

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. This article from Semiengineering highlights how much verification needs to be done, when to do it, and how to do it more effectively.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Synopsys Unveils Breakthrough Parallel Simulation Performance Technology for VCS

Synopsys, Inc. has introduced a breakthrough simulation technology which leverages fine-grained parallelism and the latest advancements in CPU and GPU architectures & enables a high simulation speed for RTL designs and for gate-level designs.

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Find out how T&VS Services are driving a continuous need for innovation in simulation performance.

The Secret To Reaching Rapid Verification Closure

This article from Semiengineering describes how to reduce RTL verification time in order to meet aggressive schedules with increased functionality & more productivity and describes how to achieve 100% RTL Functional and Code Coverage.

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Find out how T&VS has enabled clients to improve the quality of their outgoing IP through advanced verification techniques.