Tutorial for Connecting Questa® VIP into the Processor Verification Flow

VIPs play a very important role in the verification flow of modern SoCs. They can check the correctness of communication over system buses and provide master, slave, decoder, or arbiter components if these are missing in the verification set-up. This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification [...]

2018-01-29T05:56:44+00:00 29th January, 2018|Blog, Thought Leadership|

The Verification Times are Changing

Larger, more complex designs with more software and hardware require new verification solutions that target the associated technological challenges. This article from Chip Design outlines how design and verification flows are changing and developing through the ages. Read More Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their [...]

2017-05-04T07:03:58+00:00 4th May, 2017|Blog, Thought Leadership|

Multiple Dimensions Of Low-Power Verification With Portable Stimulus

Verification of low-power SoC designs is a challenging task that benefits from as much automation as possible. With or without a UPF specification file, portable stimulus provides an unrivaled solution with multiple dimensions of value to design and verification teams. This article from Semiengineering explores the aspects of low-power verification and discusses how portable stimulus [...]

2017-01-25T04:48:11+00:00 25th January, 2017|Blog, Thought Leadership|

USB Type-C: Verification challenges and solutions

The USB Type-C connector is versatile and already gaining traction in most of the electronic devices. As designers create new products and SoCs with USB Type-C support, they need to be aware of data path and verification of hardware/software partitioning challenges. This article from Tech Design Forum summarizes how verification IP plays an important role [...]

2017-01-24T10:06:32+00:00 24th January, 2017|Blog, Thought Leadership|

How the shift towards virtual emulation is reinvigorating pre-silicon testing

With increases in the size and complexity of today's SoC devices, verification has become the critical challenge in the development process. Verification of both hardware and software before silicon is available is becoming the norm, and requires massive tests spanning billions of cycles. Meeting this challenge requires advanced verification technologies delivering the highest performance possible [...]

2017-01-11T05:22:46+00:00 11th January, 2017|Blog, Thought Leadership|

Modeling for Analog and Mixed-Signal Verification

With growing complexity and shrinking time-to-market, mixed-signal verification is becoming an enormous challenge for designers, and improving analog and mixed-signal verification performance and quality is critical in today's modern complex SoC designs. This article from Chip Estimate outlines how to overcome the challenges of analog and mixed-signal verification in SoC designs. Read More Find out [...]

2017-01-10T05:56:52+00:00 10th January, 2017|Blog, Thought Leadership|

How SoC Design is driving constraints management and Verification?

Today, SoC designs use a large number of clock domains that run asynchronously to each other. Although the use of smaller individual clock domains helps to improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time [...]

2017-09-12T11:57:24+00:00 4th January, 2017|Blog, Thought Leadership|

Transistor level ESD verification in large SoC designs

Due to the complexity of today's System-on-chip(SoC) designs, with higher resistance of power and ground meshes, increased device density, the proper design and placement of electro-static discharge (ESD) protection circuitry has become quite critical. This article from EDN outlines the essential requirements of the ESD verification flow and describes why an efficient layout-based multi-domain ESD [...]

2016-11-04T06:01:53+00:00 4th November, 2016|Blog, Thought Leadership|

Optimizing Emulator Utilization

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs increasing the challenges of verification. As the emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software. This article from Semiengineering describes how to increase [...]

2016-08-31T06:08:01+00:00 31st August, 2016|Blog, Thought Leadership|

Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs

De-risking complex networking SoC development is no longer a remote objective; rather, it is available to all design teams today. Verification consultant, Lauro Rizzatti explains how to fill the gap gaps between Pre-Silicon Verification and Post-Silicon Validation for greater efficiency and improved debug. Read More Find out how T&VS Services help successfully fill the gap [...]

2016-12-12T04:33:13+00:00 26th August, 2016|Blog, Thought Leadership|
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