Tag Archives: SOC Design

Tutorial for Connecting Questa® VIP into the Processor Verification Flow

VIPs play a very important role in the verification flow of modern SoCs. They can check the correctness of communication over system buses and provide master, slave, decoder, or arbiter components if these are missing in the verification set-up.

This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification environments by QVIP Configurator and Questa® VIP (QVIP) components and summarizes the step-by-step instructions that demonstrate how to add QVIP components into processor verification environments.

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Find out how T&VS VIPs help verification engineers access to the industry’s latest protocols, interfaces and memories required to verify their SoC designs.

Dealing with Deadlocks

Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous.Rather than just integrating IP, the challenge is understanding all the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. This article from Semiengineering highlights why IP interactions is becoming essential to SoC design.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

The Verification Times are Changing

Larger, more complex designs with more software and hardware require new verification solutions that target the associated technological challenges. This article from Chip Design outlines how design and verification flows are changing and developing through the ages.

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Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

Multiple Dimensions Of Low-Power Verification With Portable Stimulus

Verification of low-power SoC designs is a challenging task that benefits from as much automation as possible. With or without a UPF specification file, portable stimulus provides an unrivaled solution with multiple dimensions of value to design and verification teams.

This article from Semiengineering explores the aspects of low-power verification and discusses how portable stimulus can address the challenges when defining a low power design methodology for real-world SoC designs.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.

USB Type-C: Verification challenges and solutions

The USB Type-C connector is versatile and already gaining traction in most of the electronic devices. As designers create new products and SoCs with USB Type-C support, they need to be aware of data path and verification of hardware/software partitioning challenges.

This article from Tech Design Forum summarizes how verification IP plays an important role in achieving the best implementation and describes how to solve the verification of hardware and software partitioning challenges for an efficient, flexible and successful implementation of USB Type-C.

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Find T&VS Verification Services and learn how to implement the Type-C Port Controller to address multiple SoC design challenges.

How the shift towards virtual emulation is reinvigorating pre-silicon testing

With increases in the size and complexity of today’s SoC devices, verification has become the critical challenge in the development process. Verification of both hardware and software before silicon is available is becoming the norm, and requires massive tests spanning billions of cycles.

Meeting this challenge requires advanced verification technologies delivering the highest performance possible to accelerate the verification process. This article from Embedded Computing describes how hardware emulation engines, primarily used for pre-silicon validation, are now seen as the hub in the verification cycle for SoC design.

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Find how T&VS Emulation Services provide comprehensive verification solutions across the entire SoC development cycle and increases the quality of the design.

Modeling for Analog and Mixed-Signal Verification

With growing complexity and shrinking time-to-market, mixed-signal verification is becoming an enormous challenge for designers, and improving analog and mixed-signal verification performance and quality is critical in today’s modern complex SoC designs. This article from Chip Estimate outlines how to overcome the challenges of analog and mixed-signal verification in SoC designs.

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Find out how T&VS successfully verifies the analog and mixed-signal designs that enables companies to make continuous improvements to their design and verification environments.

How SoC Design is driving constraints management and Verification?

Today, SoC designs use a large number of clock domains that run asynchronously to each other. Although the use of smaller individual clock domains helps to improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time consuming.

Managing and verifying design constraints presents a number of challenges to methodology developers and verification engineers.  An article from Real Intent explores how to address constraints and exceptions management across full-chip SoC designs which allows designers to reduce design cycle times and improve the quality of the design constraints.

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Find how T&VS SoC Verification Services ensures greater efficiency, improve debug, faster time-to-market, and gives design teams the ability to de-risk the challenges of complex chip designs.

Transistor level ESD verification in large SoC designs

Due to the complexity of today’s System-on-chip(SoC) designs, with higher resistance of power and ground meshes, increased device density, the proper design and placement of electro-static discharge (ESD) protection circuitry has become quite critical.

This article from EDN outlines the essential requirements of the ESD verification flow and describes why an efficient layout-based multi-domain ESD analysis and verification is required to address the needs of large SoC designs.

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Learn how T&VS help engineers address the challenges of complex SoC designs successfully.

Optimizing Emulator Utilization

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs increasing the challenges of verification. As the emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software.

This article from Semiengineering describes how to increase the emulator utilization that allows for software debug earlier in the design cycle.

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Find out how T&VS Emulation Services help you build a verification strategy that will enable customers to verify, debug and improve the performance of their SoC designs more efficiently and effectively.