With the widespread use of system-on-chip (SoC) designs, an efficient integrated circuit (IC) design and validation is now a team sport. Extensive intellectual property (IP) use, design re-use, and re-design from both internal and external sources have made successful IC design as much about efficient IP management and integration, as it is about creating new blocks and functionality. This article from Chip Design describes how IP blocks are used in the context of larger SoC designs.
Find out how T&VS solve the challenges of SoC Verification
This article from EDA Café describes how graph-based scenario models are ideal for establishing, measuring, and refining system coverage.
Learn more about Cache Coherency Verification
TVS is proud to work with Infineon, Freescale, Breker and Synopsys to bring the DVClub on Tuesday 1stDecember. The event will focus on “Coverage Closure”. You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration.
This latest DVClub event has another great line up of talks and speakers, coming from both the user and vendor communities. As always there will be plenty of time for Q&A and for networking with your industry peers.
The agenda for the event as follows:
- DVClub Europe, Tuesday 22 September, 2015
- In-Person: Bristol (New Venue*), Cambridge, Grenoble and Sophia
- Remote Access (via Internet)
- Full Program Information
Places are limited and this event is often over-subscribed so we recommend early registration.
“To cater to exponentially growing complexity and ever shrinking ‘Time to Market’, we need to find better ways to achieve our verification goals faster.” states Gaurav Gupta (Staff Design Engineer) Freescale Semiconductor Inc. at his forthcoming talk at DVClub Europe on Tuesday 1st December.
In this presentation Gaurav will explain that the distinction between IP and SoC verification is getting obscured as the dynamics of verification shift to a ‘Sub-System’ containing multiple IPs working together.
There is a clear need to make SoC verification and IP verification more ’inter-reusable’ in-order to mitigate not just the issues in modelling of environments around Standalone IPs versus actual SoC/Sub-System but also to empower system level verification environment with scalable and re-usable methodology which defines guidelines about how to handle and manage verification problems efficiently in structured manner.
It would be desirable to not just be able to port stimulus from IP verification environment to a SoC verification environment but to have SoC environment an extension of the IP verification environment.
See the full agenda and registration details here
The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events. Attendance is free and can be in-person by attending one of three European venues or via remote access. Attendance is open to all non-service provider semiconductor professionals but registration is essential as these sessions are often over-subscribed. DVClub Europe is coordinated by TVS with the support from a number of sponsors.
This article from NXP Semiconductors outlines the constraint randomized OVM based CDV methodology for SoC Verification adopted for HW SW co-verification at System Level Verification by making use of IP level verification resources and verification framework.
System-on-chip (SOC) Verification projects have a gap between simulation testbenches and hardware-software co-verification in emulation or prototypes.
Testbenches compliant with the UVM standard have no provision for running verification tests in the SOC’s embedded processors.
This article from Breker outlines how to automate the test cases to fill the SOC verification gap.
In this article Graham Bell, Vice president of Marketing, outlines today’s design teams grapple with how to keep a project on target and converging to tape-out and success when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track.
SoC verification poses many challenges through the sheer size of designs and the various mix of design IP, each operating with its own clocking scheme. Successful SoC design teams will meet the challenge of clock domain crossing verification with a solution that provides the necessary precision, throughput and ease-of-use they need. This approach will avoid a stampede of errors and late debugging that will delay the ship-out of their designs.
Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests using this platform
This EDN blog explains Cadence’s Perspec System Verifier which claims up to ten-time productivity improvement in system-on-chip verification by, among other strategies, automating some of the manual tasks when preparing system-level coverage-driven test development. It marks a shift towards software-driven verification, rather than (or, as well as) one that starts at the hardware logic level.
If you would like to review the slides and recordings of the presentations, they are now available on the TVS Website.
The Bangalore edition of the next DVClub is scheduled for mid-June. The theme will be ‘SoC Verification Challenges’. Why not register your interest and be one of the first to secure your place!
Do you have an SoC Verification story to tell and would like to share it at the next DVClub?
Contact Shyam.R for more information on how you can participate.
In this article Richard Pugh of Mentor Graphics argues that there are currently 3 main approaches to SoC Verification
- Verification IP based verification where the main focus is to verify a new piece of IP.
- FPGA-based which is useful when the hardware is stable and you are mainly spinning on the software.
- In-Circuit Emulation (where the emulation is physically attached to peripherals) which can support rapidly changing hardware and software but has the potential drawback of being tied to a lab environment with a lack of easy access.
Mentor Graphics announced in 2012 an approach which would end the reliance on external hardware devices running models of your target peripherals and instead allow you to put the emulator in your general data centre and treat it as just another computing resource.This new emulation approach, or “Virtual lab”, lets you load your target protocol on the emulator alongside your design and drive the software side of the test process from a PC where your real target OS, drivers and applications run safely inside a virtual machine.
In this article Richard Pugh outlines the “Virtual lab” approach.