Collaborative SoC Verification

With the widespread use of system-on-chip (SoC) designs, an efficient integrated circuit (IC) design and validation is now a team sport. Extensive intellectual property (IP) use, design re-use, and re-design from both internal and external sources have made successful IC design as much about efficient IP management and integration, as it is about creating new [...]

2016-04-14T05:28:00+00:00 14th April, 2016|Blog, Thought Leadership|

Register for DVClub Europe Conference “Coverage Closure” on 1 December 2015

TVS is proud to work with Infineon, Freescale, Breker and Synopsys to bring the DVClub on Tuesday 1stDecember. The event will focus on “Coverage Closure”. You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration. This latest DVClub event has another great [...]

2015-11-26T10:21:44+00:00 25th November, 2015|Active Event, Blog, Events|

Bring IP Verification Closure to SoC

“To cater to exponentially growing complexity and ever shrinking ‘Time to Market’, we need to find better ways to achieve our verification goals faster.” states Gaurav Gupta (Staff Design Engineer) Freescale Semiconductor Inc. at his forthcoming talk at DVClub Europe on Tuesday 1st December. In this presentation Gaurav will explain that the distinction between IP [...]

2015-11-17T07:02:55+00:00 17th November, 2015|Active Event, Blog, Events|

Threading the Way through SOC Verification

System-on-chip (SOC) Verification projects have a gap between simulation testbenches and hardware-software co-verification in emulation or prototypes. Testbenches compliant with the UVM standard have no provision for running verification tests in the SOC's embedded processors. This article from Breker outlines how to automate the test cases to fill the SOC verification gap.

2018-02-23T12:47:51+00:00 1st October, 2015|Blog, Thought Leadership|

SoC Verification: There is a Stampede!

In this article Graham Bell, Vice president of Marketing, outlines today’s design teams grapple with how to keep a project on target and converging to tape-out and success when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track. SoC verification poses many challenges [...]

2015-06-18T05:33:37+00:00 18th June, 2015|Blog, Thought Leadership|

Software-centric approach for complex SoC verification

Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests using [...]

2015-06-16T06:15:23+00:00 16th June, 2015|Blog, Thought Leadership|

Mentor Discuss a new approach to Verification – The Virtual lab Emulation Environment

In this article Richard Pugh of Mentor Graphics argues that there are currently 3 main approaches to SoC Verification Verification IP based verification where the main focus is to verify a new piece of IP. FPGA-based which is useful when the hardware is stable and you are mainly spinning on the software. In-Circuit Emulation (where [...]

2015-04-08T07:35:16+00:00 8th April, 2015|Blog, Thought Leadership|
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