Tag Archives: SoC

Turning Down the Voltage

Designers of large, advanced-node SoCs are grappling with a number of pressures in the quest to achieve the optimal performance and power of their designs. This has turned into a challenging balancing act between using less power, while also providing the same or greater performance and increased functionality. This article explores why the complexity of SoC is making it more difficult to combine functional performance with demands for lower power.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Portable stimulus Smooths Path to SW-driven Verification, eliminates duplication

Taking a step-wise approach to verifying interactions between embedded processors and the IPs in the rest of the design saves time by finding bugs earlier in the verification process when they’re easiest to debug and correct. Portable stimulus allows high-quality tests to be generated from test intent that is described once and retargeted to multiple environments. This article outlines how a single description of test intent, for testing access to SoC registers as a part of SoC integration testing, can be easily targeted to both UVM and embedded-software environments.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.

Raising SoC Development Productivity with Portable Stimulus

The semiconductor industry has achieved significant productivity increases by the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to reuse verification stimulus across design scope and verification engines. This article highlights why SoC development has hit a bottleneck when it comes to re-using verification stimulus.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.

Using Hardware Secure modules to protect SoCs

Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules.

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Find out how T&VS Hardware Security Services deliver secure solutions and empowers you to protect your most valuable assets

A Unified DFT Verification Methodology

In today’s fast-growing SoC, incomplete or ineffective DFT support due to poor specification or loose design practices can quickly become the critical path to making market windows and delivering products within cost restrictions.

This article highlights a unified DFT verification methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure and examine the benefits of this approach, looking at how this methodology can help bridge the widening gap between design and test.

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T&VS provides proven DFT services using industry standard tools that can reduce your time-to-market, improve your test predictability, and ensure that your silicon comes up quickly & easily.

Big Challenges, Changes for Debug

Debug is becoming much more complicated at a time when it is also becoming much more critical. Designs are more customized, and they are being used in markets where safety and security are critical. This article summarizes why chip architects and engineers are looking at new approaches to speed up and simplify debug, including continuous monitoring, error correcting strategies, and developing SoCs and ASICs that are inherently easier to debug.

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Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

Reset Verification in SoC Designs

Modern SoC designs contain a high level of complexity in the reset distribution and synchronization circuitry. Verifying that a design can be correctly reset under all modes of operation presents a significant challenge. This article explores the commonly occurring issues that are involved in reset tree verification and describes the comprehensive solutions to address these challenges.

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Find how T&VS provides services to organizations developing complex SoC based systems that require embedded hardware security and offers a comprehensive security requirements analysis and architectural specification service.

Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff

As SoC increases in complexity, one of the elements that are becoming critical is effective power estimation and correlation with silicon. Early and accurate SoC power estimation is becoming a challenge. This article from Design Reuse explains why it is imperative to develop robust methodology that provides unified framework across pre and post silicon domains for accurate power estimations and correlations.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

How to automate test from IP to SoC levels using portable stimulus

Portable stimulus seeks to raise the level of abstraction and enable the automated test of complex scenarios that emerge in subsystem- and SoC-level verification. This article highlights the role of portable stimulus at the block level and describes how portable stimulus can be used to automate test from IP to SoC levels.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.

An Incremental Approach to Reusing Automated Tests from IPs To SoCs

Portable stimulus tools help to raise the level of test description and enable modelling of scenarios that would be very challenging to create with directed and transaction-level constrained random tests. As a result, they enable automated creation of more unique tests. This article from Semiengineering highlights how to get started using portable stimulus to automate testing at the block, subsystem, and system levels.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.