Adding NoCs To FPGA SoCs

FPGAs and ASICs are two different types of chips used for programming. FPGA chip can provide the necessary flexibility but only ASIC chip can provide higher performance requirements. FPGA SoCs offer a solution which provides some performance and low power benefits of an ASIC and flexibility of a FPGA. FPGA SOC is a hybrid device [...]

2018-07-31T06:25:27+00:0031st July, 2018|Blog, Thought Leadership|

Embedded FPGAs start to take hold in SoC

Now-a-days, embedded FPGAs started to find market with telecommunications. In the beginning, market kept on changing because users were looking beyond cost to the need to support fast-moving standards. Several attempts were done to kickstart the technology, but it ran to issues of cost and density. Many SoC designers applied many ways to keep flexibility [...]

2018-07-27T06:37:55+00:0027th July, 2018|Blog, Thought Leadership|

Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

This article from Mentor Graphics explores how portable stimulus, via Accellera’s Portable Stimulus Standard (PSS), can leverage information captured in a register model to automate creation of block, subsystem, and SoC register-access tests. Read More Find out how T&VS portable stimulus specification addresses today industry verification challenges.

2018-07-12T07:06:13+00:0012th July, 2018|Blog, Thought Leadership|

Solving Six Low-Power Debug Pitfalls

Simulation-based debug challenges arise when verifying the behaviour of a power-managed SoC from the front-end design phase through the back-end implementation phase. This article summarizes the low-power debug challenges and common pitfalls, along with some ideas on how to make them easier to solve or avoid altogether. Read More Find out how T&VS services help [...]

2018-06-27T07:16:38+00:0027th June, 2018|Blog, Thought Leadership|

How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

System design companies are increasingly turning to emulators as the only verification platform with the capacity and performance to validate that their system-on-chip (SoC) and system-of-systems (SoS) designs function as intended. On an emulator, this complex SoC and SoS verification happens with the help of an advanced capability called transaction-based co-modeling. This article from Tech [...]

2018-06-20T08:13:15+00:0020th June, 2018|Blog, Thought Leadership|

Has the Time Finally Arrived for SoC Level Verification IP?

Increasing System-on-Chip (SoC) complexity has led to IP verification challenges between architecturally different processors and interface cores. This article from Chip Estimate clarifies why SoC verification IP is needed, difficulties integrating ARM and PCIe interfaces and the role of portable stimulus. Read More Find out how T&VS Verification services help to meet the challenging requirements [...]

2018-06-14T06:49:14+00:0014th June, 2018|Blog, Thought Leadership|

FPGAs Becoming More SoC-Like

Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This article describes why FPGAs are becoming more SoC-like. Read More Check out T&VS services that help you know [...]

2018-06-13T07:39:15+00:0013th June, 2018|Blog, Thought Leadership|

The Portable Stimulus Pi Contest at DAC 2018

There is a crescendo of voices speaking to portable stimulus and the value of generating more tests and improving SoC coverage. At DAC in San Francisco you’ll have an opportunity to show off your portable stimulus skills. Contestants will be chosen to compete two at a time, head-to-head, in our “First Annual Pi Contest”. Register [...]

2018-06-11T10:55:42+00:0011th June, 2018|Blog, Thought Leadership|

How to protect SoCs Using hardware secure modules

Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules Read More Find out how [...]

2018-06-06T07:48:53+00:006th June, 2018|Blog, Thought Leadership|