What Does the Future Hold in Hardware Emulation

Decades after its introduction, hardware emulation now is the preferred choice for design debugging. It satisfies all the verification objectives of a SoC design regardless of its type and application, from hardware verification and hardware/software integration to embedded software and system validation, including post-silicon validation. Verification Consultant, Lauro Rizzatti, summarizes in this article on what [...]

2018-04-26T06:00:32+00:00 26th April, 2018|Blog, Thought Leadership|

Emulation Outside the Box

This article from Semiwiki explores how the emulation system bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a design and helps optimize the design for improved performance.

2018-04-17T06:26:05+00:00 17th April, 2018|Blog, Thought Leadership|

How hardware emulation helps drones take flight

In this article, Verification Consultant, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs and outlines why drones are growing in importance and complexity with Bo Shen, founder and CTO of Artosyn Microelectronics. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a design and helps optimize the design [...]

2018-03-27T07:51:55+00:00 27th March, 2018|Blog, Thought Leadership|

A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs

A RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration.A RISC-V microprocessor can be configured in several architectural modes depending upon the target market and applications. Further, each microprocessor implementation can have different micro-architectural parameters depending upon performance, and power considerations. Arun Chandra & Dr. Mike Bartley [...]

2018-03-13T07:24:16+00:00 13th March, 2018|Blog, Thought Leadership|

The Hierarchical architecture of an embedded FPGA

The most powerful approach to managing the complexity of current SoC hardware is the identification of hierarchical instances with which to assemble the design. The development of the hierarchical design representation requires judicious assessment of the component definitions. This article from Semiwiki highlights the typical hierarchical architecture of an embedded FPGA. Read More Check out T&VS services [...]

2018-03-08T10:01:48+00:00 8th March, 2018|Blog, Thought Leadership|

Hardware Emulation — What Does the Future Hold?

Three decades after its introduction, hardware emulation now is the preferred choice for design debugging. It is powerful and flexible, provides simulation-like design visibility and scales with the increasing capacity of modern and future chips. It satisfies all the verification objectives of a SoC design regardless of its type and application, from hardware verification and [...]

2018-03-06T06:44:18+00:00 6th March, 2018|Blog, Thought Leadership|

Hardware Emulation in Mid-Life — Moving to Center Stage

In the early days, hardware emulation was used for only the most sophisticated, challenging designs at the time. Verification Consultant, Lauro Rizzatti, describes how hardware emulation moved into the new millennium with a new outlook on SoC chip design verification. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a [...]

2018-02-27T05:19:09+00:00 27th February, 2018|Blog, Thought Leadership|

Turning Down the Voltage

Designers of large, advanced-node SoCs are grappling with a number of pressures in the quest to achieve the optimal performance and power of their designs. This has turned into a challenging balancing act between using less power, while also providing the same or greater performance and increased functionality. This article explores why the complexity of [...]

2018-02-20T03:46:13+00:00 20th February, 2018|Blog, Thought Leadership|

Portable stimulus Smooths Path to SW-driven Verification, eliminates duplication

Taking a step-wise approach to verifying interactions between embedded processors and the IPs in the rest of the design saves time by finding bugs earlier in the verification process when they’re easiest to debug and correct. Portable stimulus allows high-quality tests to be generated from test intent that is described once and retargeted to multiple [...]

2018-02-15T06:04:14+00:00 15th February, 2018|Blog, Thought Leadership|

Raising SoC Development Productivity with Portable Stimulus

The semiconductor industry has achieved significant productivity increases by the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to reuse verification stimulus [...]

2018-02-13T11:22:06+00:00 13th February, 2018|Blog, Thought Leadership|
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