This article from Mentor Graphics explores how portable stimulus, via Accellera’s Portable Stimulus Standard (PSS), can leverage information captured in a register model to automate creation of block, subsystem, and SoC register-access tests. Read More Find out how T&VS portable stimulus specification addresses today industry verification challenges.
Simulation-based debug challenges arise when verifying the behaviour of a power-managed SoC from the front-end design phase through the back-end implementation phase. This article summarizes the low-power debug challenges and common pitfalls, along with some ideas on how to make them easier to solve or avoid altogether. Read More Find out how T&VS services help [...]
System design companies are increasingly turning to emulators as the only verification platform with the capacity and performance to validate that their system-on-chip (SoC) and system-of-systems (SoS) designs function as intended. On an emulator, this complex SoC and SoS verification happens with the help of an advanced capability called transaction-based co-modeling. This article from Tech [...]
Increasing System-on-Chip (SoC) complexity has led to IP verification challenges between architecturally different processors and interface cores. This article from Chip Estimate clarifies why SoC verification IP is needed, difficulties integrating ARM and PCIe interfaces and the role of portable stimulus. Read More Find out how T&VS Verification services help to meet the challenging requirements [...]
Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This article describes why FPGAs are becoming more SoC-like. Read More Check out T&VS services that help you know [...]
There is a crescendo of voices speaking to portable stimulus and the value of generating more tests and improving SoC coverage. At DAC in San Francisco you’ll have an opportunity to show off your portable stimulus skills. Contestants will be chosen to compete two at a time, head-to-head, in our “First Annual Pi Contest”. Register [...]
Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules Read More Find out how [...]
Decades after its introduction, hardware emulation now is the preferred choice for design debugging. It satisfies all the verification objectives of a SoC design regardless of its type and application, from hardware verification and hardware/software integration to embedded software and system validation, including post-silicon validation. Verification Consultant, Lauro Rizzatti, summarizes in this article on what [...]
This article from Semiwiki explores how the emulation system bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a design and helps optimize the design for improved performance.
In this article, Verification Consultant, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs and outlines why drones are growing in importance and complexity with Bo Shen, founder and CTO of Artosyn Microelectronics. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a design and helps optimize the design [...]