Using IP in a SoC Compliant with ISO 26262

The ISO standards body has already put in place a functional safety compliance specification known as ISO 26262, so engineers working at automotive companies have a clear idea how to document their processes to ensure that consumers are going to be safe. This article explains how to use IP in a SoC compliant with ISO 26262. [...]

2018-11-28T08:25:06+00:0028th November, 2018|Blog, Thought Leadership|

The challenges of Automotive Functional Safety Verification

Functional safety verification is one of the most critical issues for automobile development. Verification engineers developing an SoC for the automotive market must show that it doesn’t have functional safety issues, even if the SoC enters an unexpected state. Here’s the article from Tech Design Forum explains how to tackle the safety verification task ensuring [...]

2018-10-12T05:44:22+00:0012th October, 2018|Blog, Thought Leadership|

Adding NoCs To FPGA SoCs

FPGAs and ASICs are two different types of chips used for programming. FPGA chip can provide the necessary flexibility but only ASIC chip can provide higher performance requirements. FPGA SoCs offer a solution which provides some performance and low power benefits of an ASIC and flexibility of a FPGA. FPGA SOC is a hybrid device [...]

2018-07-31T06:25:27+00:0031st July, 2018|Blog, Thought Leadership|

Embedded FPGAs start to take hold in SoC

Now-a-days, embedded FPGAs started to find market with telecommunications. In the beginning, market kept on changing because users were looking beyond cost to the need to support fast-moving standards. Several attempts were done to kickstart the technology, but it ran to issues of cost and density. Many SoC designers applied many ways to keep flexibility [...]

2018-07-27T06:37:55+00:0027th July, 2018|Blog, Thought Leadership|

Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

This article from Mentor Graphics explores how portable stimulus, via Accellera’s Portable Stimulus Standard (PSS), can leverage information captured in a register model to automate creation of block, subsystem, and SoC register-access tests. Read More Find out how T&VS portable stimulus specification addresses today industry verification challenges.

2018-07-12T07:06:13+00:0012th July, 2018|Blog, Thought Leadership|

Solving Six Low-Power Debug Pitfalls

Simulation-based debug challenges arise when verifying the behaviour of a power-managed SoC from the front-end design phase through the back-end implementation phase. This article summarizes the low-power debug challenges and common pitfalls, along with some ideas on how to make them easier to solve or avoid altogether. Read More Find out how T&VS services help [...]

2018-06-27T07:16:38+00:0027th June, 2018|Blog, Thought Leadership|

How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

System design companies are increasingly turning to emulators as the only verification platform with the capacity and performance to validate that their system-on-chip (SoC) and system-of-systems (SoS) designs function as intended. On an emulator, this complex SoC and SoS verification happens with the help of an advanced capability called transaction-based co-modeling. This article from Tech [...]

2018-06-20T08:13:15+00:0020th June, 2018|Blog, Thought Leadership|

Has the Time Finally Arrived for SoC Level Verification IP?

Increasing System-on-Chip (SoC) complexity has led to IP verification challenges between architecturally different processors and interface cores. This article from Chip Estimate clarifies why SoC verification IP is needed, difficulties integrating ARM and PCIe interfaces and the role of portable stimulus. Read More Find out how T&VS Verification services help to meet the challenging requirements [...]

2018-06-14T06:49:14+00:0014th June, 2018|Blog, Thought Leadership|

FPGAs Becoming More SoC-Like

Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This article describes why FPGAs are becoming more SoC-like. Read More Check out T&VS services that help you know [...]

2018-06-13T07:39:15+00:0013th June, 2018|Blog, Thought Leadership|