Embedded software is becoming more critical in managing the power and performance of complex designs, but so far there is no consensus about the best way to approach it and that’s creating problems.
This article from Semiengineering highlights the approach to overcome the challenges of verifying the embedded software and explores the comprehensive coverage of verification and debugging techniques for embedded software, which is used in safety critical applications.
Find how T&VS Verification Services ensures greater efficiency, improve debug, faster time-to-market, and gives design teams the ability to de-risk the challenges of complex chip designs.
Embedded software is becoming more critical in managing the power and performance of complex designs, but so far there is no consensus about the best way to approach it and that’s creating problems. This article from Semiengineering outlines the approach to overcome the challenges of verifying the embedded software and explores the comprehensive coverage of verification and debugging techniques for embedded software, which is used in safety critical applications.
Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.
The goal of the SAFEPOWER project (an EU Horizon 2020 programme) is to enable the development of low power mixed-criticality systems through the provision of a reference architecture, platforms and tools to facilitate the development, testing, and validation of these kinds of systems according to the market needs.
Simon Davidmann of Imperas Software, presented an overview of SAFEPOWER – Xilinx Zynq 7000 device, hypervisor, OS, applications and then focused on the software architecture which help address safety critical aspects of the platform, and outlined about the software simulation tools (for example for power estimation and management) and software verification at the DVClub Europe Conference which took place on 29th November 2016.
The Presentation Slides and Videos are available now!
Many organizations developing avionics software still suffer from poor verification practices. Certain verification techniques can benefit those seeking compliance to avionics certification standards through a strategy of defect avoidance.
This article from Cadence explains the results of a survey involving verification engineers from 7 major Cadence customers located in North America, Japan, India and Europe. The survey highlighted that process nodes mostly ranged from 28nm to 45nm and cited the top reasons for running gate-level simulation. A separate question about DFT simulation revealed that about half of respondents use this technique to verify scan chains.
DVClub Bangalore is back and this time the theme is “Hardware Software Co-Verification”.
If you are a technology user, developer or industry expert looking to discuss some of the recent trends in co-verification then don’t miss this unique opportunity. The event will include co-verification and traditional techniques like simulation acceleration, emulation and prototyping.
Date: 9 April 2015, Thursday
Venue:Cadence Office, Ecospace, Bangalore
Time:9:30 AM to 12:45 PM
Plan now to join us at the event by registering for FREE. You can also register via Remote access.
Please feel free to forward this to your colleagues and stay tuned for further updates.
Bristol, UK, 15th July, 2014 – TVS, a leader in software test and hardware verification solutions, today announced that it has established a unit software testing strategy for Creo Medical, a manufacturer of clinically innovative medical devices, thereby highlighting the breadth of its operations and underpinning the trust placed in it by customers working in critical fields.
The slides and recordings from the second “Intelligent Testing” Conference are now available on our website. You can listen to the keynote from Rolls Royce talking about using agile in embedded software development and static analysis plus many more:
- Intelligent Testing in Complex Environments
- Get Yourself Covered
- Static Analysis – What, Why, Where, When, Who and How
- Agile and CI for Embedded Software and Tool Development
- Static Analysis and Formal Proof for Software Systems using the MALPAS Toolset
- Virtual Platform Software Simulation for Enhanced Multi-core Software Verification
- Harnessing Sophisticated Assertion Checking Through Runtime Testing
The presentations were informative and worth reviewing if you couldn’t attend the conference (or hearing again).
Read about ” Harnessing Sophisticated Assertion Checking Through Runtime Testing ” : Slides Video Presentation
Read about Lauterbach Presentation: Slides Video Presentation