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SVA Alternative for Complex Assertions

Assertion-based verification has been an integral part of modern-day design verification. Concurrent SVA is a powerful assertion language that expresses the definition of properties in a concise set of notations and rules. This article explains how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks and provides examples that [...]

2018-04-04T08:33:28+00:004th April, 2018|Blog, Thought Leadership|