Tag Archives: System Verilog

Dual Focus Will Help Adoption

One of the great things associated with the development of a standard, such as the Portable Stimulus Standard (PSS), is that it brings together various stakeholders. This article from EDA Café describes how the System Verilog and UVM users adopt the PSS DSL (Domain Specific Language).

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Reusable Verification Model for Motion Estimation Algorithm

Increasing functionalities of application specific integrated circuits (ASIC) require rather more efficient verification methods. This article from Design Reuse outlines how the novel verification model (VM) for low complexity motion estimation (ME) hardware architecture is used in a video encoder.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

System-Level Coverage Closure with Graph-Based Portable Stimulus

In his forthcoming talk at DVClub Europe on Tuesday 1st December, Adnan Hamid (CTO and Co-Founder) Breker Verification Systems will discuss using graph based portable stimulus in system level coverage closure.

Coverage metrics are a key for effective chip verification, but many types of coverage tend to focus on the implementation rather than the verification intent. This talk introduces system-level coverage metrics that are captured by the graph-based scenario models used to drive a portable stimulus solution as defined by Accellera.

In addition to the higher level of abstraction provided by system-level coverage, the nature of a graph means that all paths can be analyzed and closure is guaranteed for all coverage defined by the graph. It is possible to automatically generate a set of test cases that hit all system-level coverage metrics, including complete exercise of all corner cases in standard protocols. System-level coverage results can be exported as SystemVerilog coverage so that it can be merged with other metrics.

See the full agenda and registration details here

About DVClub

The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events.  Attendance is free and can be in-person by attending one of three European venues or via remote access.  Attendance is open to all non-service provider semiconductor professionals but registration is essential as these sessions are often over-subscribed.  DVClub Europe is coordinated by TVS with the support from a number of sponsors.

Metric Driven Verification of Reconfigurable Memory Controller IPs

The Metric driven controller model, along with the asynchronous comparison approach aids the reuse of the proposed memory controller verification IP for wide varieties of the Controllers. This technique can be further enhanced to build a universal verification IP for controllers which have similar functionalities that can be reused.

The article presents a method for verifying a standard SDRAM controller IP, based on UVM framework using the Object Oriented verification language System Verilog.

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Experience the DVContinuum

Experience the DVContinuum :
Oliver Bell, Intel Mobile Communications, Germany

What’s the DVContinuum?

For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November(Munich, Nov 11- 12, 2015). For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits.

Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.

The DVContinuum Anno 2015 – a Historic Perspective 

As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.
For a successful moon mission, not only the actual rocket science engineering but thorough and early verification, continuous learning by the teams and stress testing using system simulation vehicles were key factors.

Looking deeper into the story of the successful Apollo 11 landing on July20, 1969, we get very interesting insights on the importance of the right verification. As the lunar module Eagle made its landing approach to the moon, in short distance to the surface,among other related ones a computer alert 1202 was raised.

Steve Bales, the computer expert in Gene Kranz’s Mission Control team, was able to analyze the alert 1202 quickly as an “Executive overflow” alarm. This simply meant that the computer was in trouble completing its work in the available cycle time. So the right GO for landing decision was made, and no ABORT with maybe fatal consequences. Because exactly this test case was simulated upfront the Apollo 11 mission, Steve Bales was able to correctly analyze this alert so fast. Just two weeks prior to the Apollo 11 launch, simulation supervisor Dick Koos had thrown in a series of program alarms (including the 1202) during the integrated simulations for the stress testing of the flight controllers and the Apollo11 crew’s reaction. During this massive testing, the team had failed with the wrong ABORT decision– two weeks later this simulation experience became real and helped Mission Control for the right decision and supported a successful moon landing.

As you may see from this historical example, the DVContinuum addresses the ever increasing complexity, which was well mastered 50 years ago, and exemplifies the importance for our IC industry. Understanding this DVContinuum is vital to meet the requirements and to address the complexity of the “Systems of Systems” verification.Smarter abstraction techniques, automation, stimuli techniques and above all the creativity of Verification Engineers to create the appropriate simulation models in a very efficient way, will help to continuously shift the limits of verification.
If you are interested to experience the DVContinuum yourself, join us at DVCon Europe and see great examples of yesterday’s, today’s and tomorrow’s systems.Looking forward to meeting you in Munich!

If you like to share your experience with the DVContinuum, submit your paper:  DVCon Europe deadlines are May11th for your draft paper and June 1st for your Tutorial submission.

Find out more about DVCon , DVCon Europe , DVCon India

Mentor builds Simulation-Emulation bridge to ‘Verification 3.0’

Data on EDA spending suggests that emulation is the fastest growing. The EDA Consortium data shows the sector growing from $188m in 2010 to $363m in 2012.

Mentor suggests that once designs pass 250 million gates then the gate counts and complexity combined justifies the investment based on ROI. Combined with the need for hardware-software co-verification then we can start to understand the reasons behind the increased demand.

Of course, one purchased then emulation needs to be integrated into the verification strategy to maximize the ROI. The new Mentor emulation operating system, Veloce OS3, will allow a much larger number of simulation tasks to be run in emulation. For example,

  • Veloce boxes will now support SystemVerilog functional coverage, assertion-based verification and testbenches, UPF for low-power verification and both UVM and C/C++ testbenches.
  • It enables greater reuse and speeds the simulation-to-emulation port for acceleration and software test.
  • The introduction of a Unified Coverage Database providing coverage data in a common format will give a more consistent view of overall progress. This will of course also mean that emulation results can now be imported into the TVS asureSIGN tool.
  • An integrated hardware debugger, Visualizer; an integrated software debugger, Codelink; verification IP common to both Questa and Veloce; and support for virtual peripherals to move emulators from the lab into data centers.

The drivers for increased use of emulation (gate counts, complexity and HW-SW co-verification) will of course not relent and so the future for emulation is bright. It is good to see innovations from vendors look to increase ROI.

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Ever asked “Why do we need Virtual Sequences?”

If you have ever wondered why UVM environments require a virtual sequencer then this excellent article entitled “Virtual Sequences in UVM: Why, How?” posted by Hari Balisetty, Broadcom on the Synopsys blog site will go a long way to help explain this. Hari uses an example where a USB host is integrated in an AXI environment and demonstrates how we can control the USB sequencer and AXI sequencer from top-level test.

There are also a numberof other good examples in the blog page too – for example Amit Sharma of Synopsys shows how virtual sequences can be used to help verify a complex cache coherency protocol.

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Case Study: TVS helps Pactron verify complex FPGA design

pactronPactron HJPC is a leading provider of board level solutions to the semiconductor industry. Based on a qualification of TVS’ well-proven verification capabilities, Pactron chose TVS as the partner for the verification of a complex FPGA design for a financial application.

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