Tag Archives: SystemC

EDACafe interviews TVS CEO Mike Bartley

Sanjay Gangal, President of EDACafe, took time to interview TVS CEO Mike Bartley at DVCon March 2015. The interview focused on the innovative products and services being delivered by TVS in both hardware verification and software testing.

Mike had delivered a tutorial on “Requirements Driven Verification” so explained the TVS asureSIGN tool which supports this approach required for compliance to safety standards in automotive and avionics. Mike also mentioned the Instruction Stream Generator under construction at TVS for CPU/GPU and cluster developers, and the wide variety of protocols covered by the TVS VIP library.

Mike highlighted the free resources available from the TVS website from a UVM compliant SystemC library and free VIP code, through to a wide variety of presentations and papers.

Watch the interview here.

Freely available UVM SystemC library

TVS has developed a SystemC library to enable UVM verification to be performed using SystemC rather than System Verilog. This is being used by BluWireless – see here . TVS will be at DVCon Silicon Valley during March 2nd to March 5th – visit our booth if you want to find out more.

You might also be interested in the European Project “VERDI” which provides Universal Verification Methodology (UVM) in SystemC to Accellera Systems Initiative as new industry standard proposal.