High simulation times have for long been a bottleneck in functional verification. Over the years, different techniques have evolved to counter this problem some of which incorporate expensive hardware to replicate Silicon run times.
One of the innovative solutions to have emerged is Hybrid Simulation – a technique to simulate components at different levels of abstraction concurrently. In addition to drastically reducing simulation times, hybrid simulation offers other advantages as well – accelerated pre-Silicon software development, more efficient IP Verification and system level improvements.
If you are interested in knowing more about this technique, you should surely register for the Verification Futures Conference at Hotel Park Plaza, Marathahalli, Bangalore on April 16th. Vishal and Asif from Texas Instruments and Bharat from Test and Verification Solutions will present a user paper on Hybrid Simulation. In addition to detailing how Hybrid Simulation can reduce simulation run times, the paper will highlight how IP design and verification teams can benefit from this approach. The paper will also cover a real use case demonstration by TI, where a SystemC based simulator interacts with an IP in RTL form, all under TI’s IDE – Code Composer Studio.
Delegates from Intel, Qualcomm, LSI, Broadcom, Mentor Graphics, Synopsys and many others have already registered for Verification Futures Conference. Make sure you do not miss out on this opportunity to learn more about how top companies are overcoming their verification challenges. Registration is free and includes lunch and refreshments.
Speaker slots for User and Challenge paper slots at the conference are filling fast and if you would like to present on your experiences in verification, we urge you to contact us as soon as possible.
On 16th April, 2014, all roads lead to the Verification Futures Conference. Say goodbye to your Verification problems once and for all!
Last Week’s DVClub on Managing Verification Data UCIS was one of the most successful to date with almost 200 registrations. If you missed the event or if you would like to remind yourself of what was discussed on the day, the slides and video presentations are now available on the TVS website . Don’t miss the next DVClub on Monday, 7th April 2014 where we will be discussing Test Bench Qualification.
Accellera’s UCIS standard targets a critical need to bring together verification coverage information from multiple sources. The standard provides an effective mechanism for this purpose and OneSpin is able to interface its simulation and formal coverage closure technologies into the prescribed API. A range of more advanced coverage solutions may also be used to drive the database, providing extra verification clarity.
Raik Brinkmann, a co-founder of OneSpin Solutions, will give a presentation at the next European DVClub on Monday Jan 13th 2014 where he will suggest methods by which multiple coverage sources may be combined to produce comprehensive project metrics, a picture of test “completeness.”
To find out more about Riak and to register for DVClub in Bristol, Cambridge, Eindhoven, Grenoble, Sophia and by Remote Access.
Adnan Hamid, CEO of Breker, will be presenting at the next European DVClub on Monday, 13th January and will be talking about their unique coverage metrics. This talk discusses the types of system coverage that can be gathered automatically from a scenario model and considers multiple options, including UCIS, to map system coverage to traditional coverage models. The goal is for the verification team to have a comprehensive view of all coverage metrics, including the ability to roll up results to a single overall coverage assessment. Visit the website find out more about Adnan and to register for the DVClub.
Next week over 250 verification engineers will gather to discuss their verification challenges and discuss potential solutions (with another 80 online).
Verification is now the biggest task in any new semiconductor development. Engineers and manager face a range of challenges ranging from integrating data from a range of tools, through measuring test bench quality, how to find bugs earlier and improving vertical reuse, to resourcing projects. We will also look at the different challenges posed in FPGA verification. Plus the 50 challenges posed at previous conferences. You must be facing at least one of those challenges so why not come along and see if you can find a solution?
Registration is easy and free, and includes lunch, refreshments, conference bag and proceedings. We are in Munich, Reading and Sophia, with remote access too of course.
Why not register now or forward this to a colleague?
It is now just 3 weeks until Verification Futures starts a week of Verification Conferences around Europe in Germany, the UK and France. Here are 238 good reasons to attend:
- 21 Verification Challenges from 6 different companies (Broadcom, ST, Samsung, Altera, Ericsson, Infineon) plus a review of all challenges to date
- 9 leading EDA Verification vendors (Synopsys, Mentor, Cadence, Jasper, Doulos, OneSpin, Breker, Aldec and Real Intent)
- 8 user papers
Over 200 registrations to date and still rising.
Registration is free for Reading and Sophia including free lunch, refreshments, conference bag and proceedings. It gives you the chance to catch up with all of the vendors in one place in one day plus other verification engineers.
Appropriately titled ‘The Best Of Verification‘, it provides you a round-up of the best news from the Hardware Verification world. Have a good time reading the first edition and do provide your feedback. You can read it by following the links or get it regularly by following us on twitter @testandverif
A unique opportunity to hear the latest “state of the industry”
Mike Bartley will give a brief overview of the Verification Challenges faced by 15 semiconductor companies from Europe and India.
Harry Foster will highlight today’s emerging verification trends to provide a fascinating insight into the state of our industry. This allows you to benchmark your verification methodology against the rest of the industry.
You can join in both discussions by registering here.
Mike Bartley will join Harry Foster at the forthcoming DVClub on April 8th. He will be presenting the major verification challenges reported at the various Verification Challenge conferences – from UK, France, Germany and India. This gives a unique insight into the challenges seen by a wide variety of semiconductor companies around the world.
Harry Foster will highlight the key findings from the 2012 Wilson Research Group Functional Verification Study. Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. Harry will provides his unique interpretation and analysis behind today’s emerging verification trends to provide a fascinating insight into the state of pour industry.
You can join in both discussions by registering here
The first DVClub of 2013 takes place a week today on Monday 14th January starting at 11.30am GMT. We’ll be discussing Open Source Verification Tools with presentations from Wilson Snyder (on Verilator), Dag Arneat Braend (Atmel – Verilator users), Maksim Jenihhin (Tallin University of Technology, Estonia) and Rich Porter (Design & Verification Engineer). You can attend physically in Bristol, Cambridge, Grenoble and Eindhoven or remotely via Webinar. To join in the discussion and for more details, go to: