Is Hybrid simulation the panacea for Verification problems?

High simulation times have for long been a bottleneck in functional verification.  Over the years, different techniques have evolved to counter this problem some of which incorporate expensive hardware to replicate Silicon run times. One of the innovative solutions to have emerged is Hybrid Simulation – a technique to simulate components at different levels of [...]

2015-01-19T13:34:35+00:00 4th March, 2014|Events, Hardware Verification, TVS-India|

Watch Five Talks on Using UCIS from DVClub Europe

Last Week’s DVClub on Managing Verification Data UCIS was one of the most successful to date with almost 200 registrations.  If you missed the event or if you would like to remind yourself of what was discussed on the day, the slides and video presentations are now available on the TVS website .  Don’t miss [...]

2015-01-19T13:36:02+00:00 21st January, 2014|Events, Hardware Verification, TVS-Bristol, TVS-France, TVS-India|

Leveraging UCIS for Simulation and Formal Verification Closure

Accellera's UCIS standard targets a critical need to bring together verification coverage information from multiple sources.  The standard provides an effective mechanism for this purpose and OneSpin is able to interface its simulation and formal coverage closure technologies into the prescribed API.  A range of more advanced coverage solutions may also be used to drive [...]

2015-01-19T13:37:26+00:00 27th December, 2013|Events, Hardware Verification, TVS-Bristol, TVS-France|

Mapping System Coverage Metrics to Traditional Coverage Models

Adnan Hamid, CEO of Breker, will be presenting at the next European DVClub on Monday, 13th January and will be talking about their unique coverage metrics.   This talk discusses the types of system coverage that can be gathered automatically from a scenario model and considers multiple options, including UCIS, to map system coverage to traditional [...]

2015-01-19T13:41:09+00:00 18th December, 2013|Events, Hardware Verification|

What is the Collective Noun for 250 Verification Engineers?

Next week over 250 verification engineers will gather to discuss their verification challenges and discuss potential solutions (with another 80 online). Verification  is now the biggest task in any new semiconductor development.  Engineers and manager face a range of challenges ranging from integrating data from a range of tools, through measuring test bench quality, how [...]

2015-01-19T13:47:46+00:00 14th November, 2013|Events, Hardware Verification, TVS-Bristol, TVS-France|

238 Good Reasons to Attend Verification Futures 2013

It is now just 3 weeks until Verification Futures starts a week of Verification Conferences around Europe in Germany, the UK and France.  Here are 238 good reasons to attend: 21 Verification Challenges from 6 different companies (Broadcom, ST, Samsung, Altera, Ericsson, Infineon) plus a review of all challenges to date 9 leading EDA Verification [...]

2015-01-19T13:55:03+00:00 30th October, 2013|Hardware Verification, TVS-Bristol, TVS-France|

Benchmark your verification challenges and methodology

A unique opportunity to hear the latest “state of the industry” Mike Bartley will give a brief overview of the Verification Challenges faced by 15 semiconductor companies from Europe and India. Harry Foster will highlight today's emerging verification trends to provide a fascinating insight into the state of our industry. This allows you to benchmark [...]

DVClub Monday 14th January – one week to go!

The first DVClub of 2013 takes place a week today on Monday 14th January starting at 11.30am GMT. We'll be discussing Open Source Verification Tools with presentations from Wilson Snyder (on Verilator), Dag Arneat Braend (Atmel – Verilator users), Maksim Jenihhin (Tallin University of Technology, Estonia) and Rich Porter (Design & Verification Engineer). You can [...]

2013-01-07T12:34:24+00:00 7th January, 2013|Hardware Verification|
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