DVClub is coming to Bangalore on 19th June. This time, the focus is on SCE-MI based verification environments. SCE-MI transactors for protocols and interfaces like USB, PCI express and Ethernet can reduce verification turnaround times drastically. Register now and experience the benefits of incorporating SCE-MI transactors into your verification environment.
Mr. Surinder Sood from Samsung India Software operations is among the presenters. The event is open to Verification professionals with 3+ years of experience. Those unable to attend can participate via webinar.
DVClub is a unique platform to discuss trends and explore challenges in design and verification. You can find presentations from past DVClubs here.
With only 50 seats available, registrations are running out fast. Block your calendars between 7:00 pm and 9:00 pm on 19th June. Make sure you book your slot today.
A unique opportunity to hear the latest “state of the industry”
Mike Bartley will give a brief overview of the Verification Challenges faced by 15 semiconductor companies from Europe and India.
Harry Foster will highlight today’s emerging verification trends to provide a fascinating insight into the state of our industry. This allows you to benchmark your verification methodology against the rest of the industry.
You can join in both discussions by registering here.
With only six days left for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, have you booked your seat yet?
Would you want to miss out on an opportunity to interact with senior Verification professionals from ARM, Samsung, NXP, Broadcom, Cadence, Synopsys, Mentor Graphics, Aldec, Doulos, Breker systems, Maxlinear and many more all in one place? Register now!
Confirmed attendees include Verification Managers, Architects, Project Managers and Verification leads among others. The average experience range of registrations is 5+ years. The response till now has been overwhelming and over 500 people have already registered!
To book your slot, all you need to do is register yourself on our website and we will confirm your booking. See you at the event!
If you haven’t yet registered for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, do it now!
We have an exciting array of speakers from Broadcom, NXP, Aldec, Mentor Graphics, Synopsys, Cadence, Breker Systems and Doulos among others. They will be covering a wide range of topics encompassing the Verification spectrum.
Managers can benefit from Broadcom’s user paper on reducing chip level verification effort and NXP’s challenge paper on developing a scalable Verification environment. Breker systems will present on generation and visualization of multi-Threaded multi-core testcases.
For those interested in exploring trends in Verification, we have papers on Standard Co-emulation Modeling Interface (SCE-MI) and technology evolution in Functional Verification. Mr. John Aynsley from Doulos considers the feasibility of UVM adoption and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. Test and Verification solutions will be presenting on ARM-based SoC verification.
If you are facing any challenges in Verification closure, this is the place to be! Register now for live participation.
Harry Foster, Chief Scientist at Mentor, will be presenting the results of his analysis of the 2012 survey on verification techniques and trends at this next DVClub on 8th April. Every two years Harry provides a huge insight into the way our verification industry is evolving. It’s an invaluable chance to measure yourself against the wider industry. You can join Harry in Bristol or listen online with other engineers in Cambridge, Eindhoven, Grenoble, Sophia or from your own desk. To join in the discussion go to:
On 19th March, all roads lead to the Verification Futures Conference at Hotel Royal Orchid, Bangalore. With many Verification specialists and industry giants already confirming participation, this event is a must-attend for Verification professionals. What’s more, it is completely free!
Mr. Vikas Gautam, the Director of Corporate Application Engineering, Asia Pacific, Synopsys will open the proceedings. This will be followed by 3 exciting Challenge papers which will chart out the most common challenges faced in Verification closure today.
Dr. Mike Bartley, the CEO and founder of Test and Verification Solutions, will then recapture the challenges presented at the European Verification Futures Conference held in UK, France and Germany last November.
Also lined up are presentations by Mr. Jacek Majkowski from Aldec on Standard Co-Emulation Modeling Interface (SCE-MI), Mr. Naresh Ramachandran from Cadence on System and Soc Verification Trends and Mr. Mark Olen from Mentor Graphics on technology evolution in Functional Verification.
Broadcom will present a user paper that will focus on reducing chip level verification effort by optimizing gate level simulation and package-aware testbenches. For those aiming to develop a scalable verification framework, we have a presentation by NXP focusing on techniques to reduce verification turnaround times at module, sub-system and system levels.
Sounds exciting, huh? Wouldn’t you like some help to solve your Verification problems in one place? Register now!
If you are a Verification professional, you cannot afford to miss the Verification Futures conference on 19th March 2013 at Hotel Royal Orchid, Bangalore. The who’s-who of the Verification industry will be in attendance presenting, discussing and resolving those complex verification problems that you always wanted a solution to.
Broadcom will be presenting a user paper on reducing chip level verification effort by optimizing gate level simulation runs and using package aware testbenches. The novel techniques suggested in this paper make it is a must-attend for Verification managers aiming to achieve quicker verification closure times.
From NXP, Mr. Sainath will present a challenge paper that provides insights into reducing verification turnaround times at module, sub-system and system levels. This paper will be very useful to those aiming to develop a scalable, co-verification enabled system level verification environment.
We also have Verification specialists, Mr. Mark Olen from Mentor Graphics and Mr. Jacek Majkowski from Aldec presenting on two exciting topics – Technology evolution in Functional Verification and Standard Co-Emulation Modeling Interface (SCE-MI) respectively. From the EDA side, Cadence and Synopsys have already confirmed participation.
With over 180 senior Verification professionals already expressing interest in participation, seats are running out fast. For those unable to attend the event live, we are providing webinar facility also.
Put an end to your verification problems! Register now!
After a resounding success in Europe in 2012, Verification Futures is finally coming to India! This free event is a one-stop-shop for Managers and Senior Engineers to not only discuss and resolve contemporary Verification challenges but also acquaint themselves with the latest Verification trends. What’s more, leading EDA vendors and experts present Verification best practices and lessons learned from executing a multitude of complex Verification projects!
19th March – Bangalore, India
Do not miss this unique opportunity! Register now!
Don’t forget that the event is also open to junior engineers via remote access!
UKTI publishes a success story all about TVS’s operations in India. You can share our journey titled “Booming Business in India”.
UVM is now the defacto verification methodology for our industry. But how do you find the time to learn it given your current commitments?
Doulos, supplier of best in class training, is working with TVS, a specialist verification company, to help you solve this problem. We held a DVClub in Bangalore on 22nd November 2012.
Details of the talk and access to the recording is here.