Tag Archives: TVS India

Facing verification challenges in automotive chips?

At the second edition of Verification Futures in Bangalore on May 13th, Saravanan, Principal Engineer at Microchip is presenting a scoreboard design for reuse across Media Oriented Systems Transport (MOST) protocols. If you are working on automotive chips, this presentation is a must-attend! MOST technology, which is used in almost all the major car brands worldwide including Audi, BMW, Hyundai, Jaguar, Land Rover, is the de-facto standard for multimedia and infotainment networking in the autoothmotive industry.

Saravanan’s presentation will address how some of the complex verification challenges created by widespread adoption of the MOST protocol can be mitigated by verification components reuse. In addition to Saravanan’s presentation, there will also be papers on other exciting topics like Prototyping challenges, AMS challenges, Hybrid Simulation and DV flow empowerment by UVM. Do not miss out on this opportunity to get acquainted with these verification trends. Register now! Our past conferences have generated some interesting insights about where verification technology is headed.

You can find a summary of our 2013 series of conferences in Europe and India here. This time, the event will be sponsored by top EDA vendors like Synopsys, Mentor Graphics, Jasper, Atrenta and Real Intent. With delegates from leading semiconductor companies like Intel, Qualcomm, Broadcom, Nvidia, IMC, AMD, PMC Sierra, LSI etc. already confirming participation, this is an event you wouldn’t want to miss! Block your calendars now! Registration is completely free and we are accepting webinar bookings too!

Verification Futures India 13th May 2014

Verification Futures, returning to Bangalore on 13th May 2014, is a one-stop-shop that offers you the opportunity to network with Verification specialists and all of the major verification EDA vendors in the same venue.

Venue: Hotel Park Plaza, 90-4 Marathahalli/Outer Ring Road, Bangalore, Karnataka – 560037

Verification specialists from a number of product companies will share their top Verification challenges. In the past three years of Verification Futures, we have seen over 70 challenges from more than 20 presenters . There will also be papers from users from who have solved their own challenges. This time, we already have more than 200 confirmed participants with speakers presenting on diverse topics like Hybrid Simulation, AMS Verification Challenges and Generic ABCML Channel Scoreboard. Many of the top EDA vendors are also expected to be in attendance.

If you are a Verification professional, this a unique opportunity to acquaint yourself with current verification challenges and how others are solving them. Book now!  The conference sold out in 2013 and we had to disappoint those who didn’t register early. Don’t forget that the conference is also available by remote access for those who can’t attend!

DVClub in Bangalore on 19th June

DVClub is coming to Bangalore on 19th June. This time, the focus is on SCE-MI based verification environments. SCE-MI transactors for protocols and interfaces like USB, PCI express and Ethernet can reduce verification turnaround times drastically. Register now and experience the benefits of incorporating SCE-MI transactors into your verification environment.

Mr. Surinder Sood from Samsung India Software operations is among the presenters. The event is open to Verification professionals with 3+ years of experience. Those unable to attend can participate via webinar.

DVClub is a unique platform to discuss trends and explore challenges in design and verification. You can find presentations from past DVClubs here.

With only 50 seats available, registrations are running out fast. Block your calendars between 7:00 pm and 9:00 pm on 19th June. Make sure you book your slot today.


Benchmark your verification challenges and methodology

A unique opportunity to hear the latest “state of the industry”

Mike Bartley will give a brief overview of the Verification Challenges faced by 15 semiconductor companies from Europe and India.

Harry Foster will highlight today’s emerging verification trends to provide a fascinating insight into the state of our industry. This allows you to benchmark your verification methodology against the rest of the industry.

You can join in both discussions by registering here.


DVClub to present global overview of hardware verification

Mike Bartley will join Harry Foster at the forthcoming DVClub on April 8th. He will be presenting the major verification challenges reported at the various Verification Challenge conferences – from UK, France, Germany and India. This gives a unique insight into the challenges seen by a wide variety of semiconductor companies around the world.

Harry Foster will highlight the key findings from the 2012 Wilson Research Group Functional Verification Study. Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  Harry will provides his unique interpretation and analysis behind today’s emerging verification trends to provide a fascinating insight into the state of pour industry.

You can join in both discussions by registering here


Less than a week left – Verification Futures Conference 2013

With only six days left for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, have you booked your seat yet?

Would you want to miss out on an opportunity to interact with senior Verification professionals from ARM, Samsung, NXP, Broadcom, Cadence, Synopsys, Mentor Graphics, Aldec, Doulos, Breker systems, Maxlinear and many more all in one place? Register now!

Confirmed attendees include Verification Managers, Architects, Project Managers and Verification leads among others. The average experience range of registrations is 5+ years. The response till now has been overwhelming and over 500 people have already registered!

To book your slot, all you need to do is register yourself on our website and we will confirm your booking. See you at the event!


Last few days to register – Verification Futures Conference 2013

If you haven’t yet registered for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, do it now!

We have an exciting array of speakers from Broadcom, NXP, Aldec, Mentor Graphics, Synopsys, Cadence, Breker Systems and Doulos among others. They will be covering a wide range of topics encompassing the Verification spectrum.

Managers can benefit from Broadcom’s user paper on reducing chip level verification effort and NXP’s challenge paper on developing a scalable Verification environment. Breker systems will present on generation and visualization of multi-Threaded multi-core testcases.

For those interested in exploring trends in Verification, we have papers on Standard Co-emulation Modeling Interface (SCE-MI) and technology evolution in Functional Verification. Mr. John Aynsley from Doulos considers the feasibility of UVM adoption and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. Test and Verification solutions will be presenting on ARM-based SoC verification.

If you are facing any challenges in Verification closure, this is the place to be! Register now for live participation.


Next DVClub – Monday 8th April 2013

Harry Foster, Chief Scientist at Mentor, will be presenting the results of his analysis of the 2012 survey on verification techniques and trends at this next DVClub on 8th April. Every two years Harry provides a huge insight into the way our verification industry is evolving. It’s an invaluable chance to measure yourself against the wider industry. You can join Harry in Bristol or listen online with other engineers in Cambridge, Eindhoven, Grenoble, Sophia or from your own desk. To join in the discussion go to:



Help to solve your verification problems

On 19th March, all roads lead to the Verification Futures Conference at Hotel Royal Orchid, Bangalore. With many Verification specialists and industry giants already confirming participation, this event is a must-attend for Verification professionals. What’s more, it is completely free!

Mr. Vikas Gautam, the Director of Corporate Application Engineering, Asia Pacific, Synopsys will open the proceedings. This will be followed by 3 exciting Challenge papers which will chart out the most common challenges faced in Verification closure today.

Dr. Mike Bartley, the CEO and founder of Test and Verification Solutions, will then recapture the challenges presented at the European Verification Futures Conference held in UK, France and Germany last November.

Also lined up are presentations by Mr. Jacek Majkowski from Aldec on Standard Co-Emulation Modeling Interface (SCE-MI), Mr. Naresh Ramachandran from Cadence on System and Soc Verification Trends and Mr. Mark Olen from Mentor Graphics on technology evolution in Functional Verification.

Broadcom will present a user paper that will focus on reducing chip level verification effort by optimizing gate level simulation and package-aware testbenches. For those aiming to develop a scalable verification framework, we have a presentation by NXP focusing on techniques to reduce verification turnaround times at module, sub-system and system levels.

Sounds exciting, huh? Wouldn’t you like some help to solve your Verification problems in one place? Register now!

Resolve your verification problems – Verification Futures India 2013

If you are a Verification professional, you cannot afford to miss the Verification Futures conference on 19th March 2013 at Hotel Royal Orchid, Bangalore. The who’s-who of the Verification industry will be in attendance presenting, discussing and resolving those complex verification problems that you always wanted a solution to.

Broadcom will be presenting a user paper on reducing chip level verification effort by optimizing gate level simulation runs and using package aware testbenches. The novel techniques suggested in this paper make it is a must-attend for Verification managers aiming to achieve quicker verification closure times.

From NXP, Mr. Sainath will present a challenge paper that provides insights into reducing verification turnaround times at module, sub-system and system levels. This paper will be very useful to those aiming to develop a scalable, co-verification enabled system level verification environment.

We also have Verification specialists, Mr. Mark Olen from Mentor Graphics and Mr. Jacek Majkowski from Aldec presenting on two exciting topics – Technology evolution in Functional Verification and Standard Co-Emulation Modeling Interface (SCE-MI) respectively. From the EDA side, Cadence and Synopsys have already confirmed participation.

With over 180 senior Verification professionals already expressing interest in participation, seats are running out fast. For those unable to attend the event live, we are providing webinar facility also.

Put an end to your verification problems! Register now!