Tag Archives: UPF

Understanding the UPF Power Domain and Domain Boundary

Power domains are the fundamental parts of UPF constructions. All other predominant factors that are used to completely define the UPF are established around the power domain boundaries. Hence, the UPF power domain is a collection of instances that are treated as a group for power-management purposes.

The interface of a power domain is the union of the upper boundary and the lower boundary of the power domain. This article from Mentor Graphics describes the importance of UPF power domain and domain boundary.

Read More


Find out how T&VS provides a methodology for incremental specification of power intent using UPF.

DVClub Europe 22 September 2015 – “Power Aware Verification”

TVS is proud to work with Mentor Graphics, ARM, Cadence, Synopsys and Breker to bring the DVClub on Tuesday 22 September. The event will focus on “Power Aware Verification “. You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration.

The agenda for the event as follows:

Event Summary:

  • DVClub Europe, Tuesday 22 September, 2015
  • In-Person: Bristol (New Venue*), Cambridge, Grenoble and Sophia
  • Remote Access (via Internet)
  • Full Program Information

Places are limited and this event is often over-subscribed so we recommend early registration.

Challenges with Power Aware Simulation and Verification Methodologies

Divyeshkumar Dhanjibhai Vora of ARM will discuss “Challenges with Power Aware Simulation and Verification Methodologies” at DVClub Europe Conference on 22 September 2015.

He discusses about proposed enhancements like integrated PA models, liberty based assertions and UPF macro support using successive refinement, to fill the quality holes in the PA simulation flow.

As the modelling complexity is increasing, it requires a thorough check to qualify the above said features in the library models.

Divyeshkumar also discusses a library based validation flow which has been developed in-house at ARM to ensure the qualification of the PA behavior of each library cell against the reference vectors.

  • Power-aware (PA) simulation overview
  • Proposed enhancements in PA simulation
  • Library based validation flow

If you want to find out more about Power Aware Simulation and Verification Methodologies, then join us on the 22nd Sept.

You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here

Static Power Intent Verification of Power State Switching Expressions

Low power architecture of a design (specified in terms of UPF/CPF) goes through a series of refinements throughout the design cycle.Therefore it is very crucial to check whether the initial low power intent remains intact in these refinement steps.

Any erroneous refinement step usually leads to functional bugs in the design, which can only be detected late in the verification cycle.

Srobona Mitra of Synopsys will discuss a static checking methodology for verifying early that the power state switching expressions in a power architecture specification are equivalent through successive stages of power intent refinement at DVClub Europe on 22 September 2015.

  • Attending the DVClub conference on September 22nd is free but places are limited so we recommend early registration.You can register here

Successive Refinement: A Methodology for Incremental Specification of Power Intent using UPF

Gabriel Chidolue, Verification Technologist at Mentor Graphics, discusses “A Methodology for Incremental Specification of Power Intent using UPF” at DVClub Europe on 22 September 2015.

Gabriel presentation will cover how to use the UPF Successive Refinement methodology in detail, how it can accelerate design and verification with a re-usable IP to System flow, and simplify the debugging of complex power management architectures.

He will illustrate these advantages by applying the methodology to an ARM® IP-based system design.

If you want to find out more about Power Intent using UPF, then join us on the 22nd Sept.

You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here

John Biggs gives invaluable insight into UPF

At DVClub Europe on July 1st, John Biggs (Chair of the IEEE1801 UPF Working Group) gave an invaluable insight to UPF both current and future.  He first reviewed the main UPF components such as Power Domains, Power Supply Network, Power State Tables, Isolation Strategies, Retention Strategies and Level Shifter Strategies.  John explained all of these with well-chosen examples.

Given John’s position at ARM, he took time to explain the UPF capability for “Successive Refinement of Design Intent” whereby an IP supplier can supply a “Constraint UPF” along with the RTL. The IP user then adds then adds a “Configuration UPF” to create a golden source for the implementation team which adds an “Implementation UPF” for synthesis etc.

John also gave an overview of the May 2013 release of the standard (UPF-2.1) highlighting the additions made.  John’s slides and a video of his presentation can be found on our website.

The rest of the DVClub was dedicated to verification of UPF designs and can also be found on our website.

[subscribe2]