Power Aware Static Verification—From Power Intent to Microarchitectural Checks of Low-Power Designs

PA-Static verification, are performed on designs that adopt certain power dissipation reduction techniques through the power intent or UPF. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structure of the design. More precisely, [...]

2018-03-30T14:54:11+00:00 30th March, 2018|Blog, Thought Leadership|

Power Aware Intent and Structural Verification of Low-Power Designs

Power aware static verificationis performed on designs that adopt certain power dissipation reduction techniques through the power intent or UPF. This article from Semiengineering describe the foundations of power aware static verification and the solution features used for its verification. Read More Find out how T&VS services help to meet the challenging requirements with respect [...]

2018-03-20T07:00:11+00:00 20th March, 2018|Blog, Thought Leadership|

Understanding the UPF Power Domain and Domain Boundary

Power domains are the fundamental parts of UPF constructions. All other predominant factors that are used to completely define the UPF are established around the power domain boundaries. Hence, the UPF power domain is a collection of instances that are treated as a group for power-management purposes. The interface of a power domain is the [...]

2017-09-06T09:33:47+00:00 13th September, 2017|Blog, Thought Leadership|

DVClub Europe 22 September 2015 – “Power Aware Verification”

TVS is proud to work with Mentor Graphics, ARM, Cadence, Synopsys and Breker to bring the DVClub on Tuesday 22 September. The event will focus on “Power Aware Verification “. You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration. The agenda [...]

2015-09-21T06:57:44+00:00 21st September, 2015|Active Event, Blog, Events|

Challenges with Power Aware Simulation and Verification Methodologies

Divyeshkumar Dhanjibhai Vora of ARM will discuss “Challenges with Power Aware Simulation and Verification Methodologies” at DVClub Europe Conference on 22 September 2015. He discusses about proposed enhancements like integrated PA models, liberty based assertions and UPF macro support using successive refinement, to fill the quality holes in the PA simulation flow. As the modelling [...]

2015-09-21T06:33:49+00:00 21st September, 2015|Active Event, Blog, Events|

Static Power Intent Verification of Power State Switching Expressions

Low power architecture of a design (specified in terms of UPF/CPF) goes through a series of refinements throughout the design cycle.Therefore it is very crucial to check whether the initial low power intent remains intact in these refinement steps. Any erroneous refinement step usually leads to functional bugs in the design, which can only be [...]

2015-09-21T04:49:53+00:00 18th September, 2015|Active Event, Blog, Events|
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