Tag Archives: Verficiation Training

TVS Advanced Verification Training Available

TVS advanced verification training uniquely combines advanced verification techniques with their application to realistic designs. Attendees get the learn advanced verification techniques and then apply them

  • Derive a test plan for a serial IP and then extend a UVM test bench to implement the tests
  • Write assertions for the IP and add them to the test bench or try to prove them using formal
  • Verify the integration of the IP into a small SoC by writing integration tests and functional level C-based tests

The course is aimed at

  • Design Verification engineers
  • Design Verification Managers
  • Design Engineers looking to cross-train to verification
  • Companies trying to move to the latest verification techniques and strategies

A practical course delivered by verification experts that can be tailored to individual company requirements.

Click here for more details or contact [email protected]

TVS is Publishing a Weekly Verification Newsletter

Appropriately titled ‘The Best Of Verification‘, it provides you a round-up of the best news from the Hardware Verification world.  Have a good time reading the first edition and do provide your feedback.  You can read it by following the links or get it regularly by following us on twitter @testandverif

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DVClub in Bangalore on 19th June

DVClub is coming to Bangalore on 19th June. This time, the focus is on SCE-MI based verification environments. SCE-MI transactors for protocols and interfaces like USB, PCI express and Ethernet can reduce verification turnaround times drastically. Register now and experience the benefits of incorporating SCE-MI transactors into your verification environment.

Mr. Surinder Sood from Samsung India Software operations is among the presenters. The event is open to Verification professionals with 3+ years of experience. Those unable to attend can participate via webinar.

DVClub is a unique platform to discuss trends and explore challenges in design and verification. You can find presentations from past DVClubs here.

With only 50 seats available, registrations are running out fast. Block your calendars between 7:00 pm and 9:00 pm on 19th June. Make sure you book your slot today.

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T&VS launches larger library of Verification IP

Test and Verification Solutions (T&VS) has announced that it has expanded its asureVIP™ library of verification IP to cover protocols in MIPI, Memories, Universal Serial IO and Communication as well as a bespoke VIP development service.

The T&VS VIP offers many advantages to the user such as access to the source code, flexible licensing agreements and protocol compliance test suites. The latter enables the engineer to more quickly demonstrate that their design complies with the standard. The tests are mapped to the protocol specification so that the user can quickly see the intention of the test. Additionally the asureVIP™ library contains traffic generators which allows the chip integrator to quickly generate traffic across the interface. Synthesisable drivers and C interfaces allow the VIP to be used in emulation using SCEMI.

The UVM compliant asureVIP™ is written in native System Verilog so that debug becomes much easier given that the user has access to the code. Mike Bartley, Chief Executive Officer, Test and Verification Solutions said, “We have been working with clients on our VIP for some time now and a lot of the VIP is proven in a number of different environments and in silicon. Research suggests that companies are expanding their use of external VIP and adoption of UVM so I expect our UVM-compliant VIP to be very popular.”

The asureVIP™ library also contains eRM compliant VIP and in addition T&VS is able to VIP on demand under flexible ownership arrangements. The T&VS agile development process also means that the VIP is delivered in a number of short “sprints” allowing the client to make an early start on their verification.

For full details of the protocols available in the asureVIP™ library then please go our VIP page.

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Less than a week left – Verification Futures Conference 2013

With only six days left for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, have you booked your seat yet?

Would you want to miss out on an opportunity to interact with senior Verification professionals from ARM, Samsung, NXP, Broadcom, Cadence, Synopsys, Mentor Graphics, Aldec, Doulos, Breker systems, Maxlinear and many more all in one place? Register now!

Confirmed attendees include Verification Managers, Architects, Project Managers and Verification leads among others. The average experience range of registrations is 5+ years. The response till now has been overwhelming and over 500 people have already registered!

To book your slot, all you need to do is register yourself on our website and we will confirm your booking. See you at the event!

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Last few days to register – Verification Futures Conference 2013

If you haven’t yet registered for the Verification Futures conference on 19th March, 2013 at Hotel Royal Orchid, Bangalore, do it now!

We have an exciting array of speakers from Broadcom, NXP, Aldec, Mentor Graphics, Synopsys, Cadence, Breker Systems and Doulos among others. They will be covering a wide range of topics encompassing the Verification spectrum.

Managers can benefit from Broadcom’s user paper on reducing chip level verification effort and NXP’s challenge paper on developing a scalable Verification environment. Breker systems will present on generation and visualization of multi-Threaded multi-core testcases.

For those interested in exploring trends in Verification, we have papers on Standard Co-emulation Modeling Interface (SCE-MI) and technology evolution in Functional Verification. Mr. John Aynsley from Doulos considers the feasibility of UVM adoption and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. Test and Verification solutions will be presenting on ARM-based SoC verification.

If you are facing any challenges in Verification closure, this is the place to be! Register now for live participation.

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Help to solve your verification problems

On 19th March, all roads lead to the Verification Futures Conference at Hotel Royal Orchid, Bangalore. With many Verification specialists and industry giants already confirming participation, this event is a must-attend for Verification professionals. What’s more, it is completely free!

Mr. Vikas Gautam, the Director of Corporate Application Engineering, Asia Pacific, Synopsys will open the proceedings. This will be followed by 3 exciting Challenge papers which will chart out the most common challenges faced in Verification closure today.

Dr. Mike Bartley, the CEO and founder of Test and Verification Solutions, will then recapture the challenges presented at the European Verification Futures Conference held in UK, France and Germany last November.

Also lined up are presentations by Mr. Jacek Majkowski from Aldec on Standard Co-Emulation Modeling Interface (SCE-MI), Mr. Naresh Ramachandran from Cadence on System and Soc Verification Trends and Mr. Mark Olen from Mentor Graphics on technology evolution in Functional Verification.

Broadcom will present a user paper that will focus on reducing chip level verification effort by optimizing gate level simulation and package-aware testbenches. For those aiming to develop a scalable verification framework, we have a presentation by NXP focusing on techniques to reduce verification turnaround times at module, sub-system and system levels.

Sounds exciting, huh? Wouldn’t you like some help to solve your Verification problems in one place? Register now!

Easier UVM Presentation now available online

Test and Verification Solutions and Doulos recently held a joint DVClub event in Bangalore, India.  Dr David Long presented on “Easier UVM”- a 90 minute presentation on the basics of System Verilog and UVM.  If you would like to review the recording please use this link.

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Verification Futures 2012 – A Resounding Success!

Following on from the success of last year’s first UK Verification conference, Verification Futures travelled across Europe this year, show-casing presentations from internationally-renowned speakers such as Harry Foster of Mentor Graphics, Janick Bergeran from Synopsis and Jacek Majkowski of Aldec.

We had over 472 participants from 200 companies in 27 countries – it’s a popular event! But of course it is about much more than just numbers, as the event is set up for user companies to outline their challenges and for the EDA vendors to respond with some solutions.

It’s been a unique opportunity for vendors to hear challenges first hand – we had 36 challenges presented across the 3 events, many are the same but this reinforces their importance. It also allows users to hear the EDA plans and provide their feedback.

On behalf of TVS I would like to extend huge thanks to our sponsors, for taking part and sharing their knowledge across these events. They are: Aldec Inc, Cadence, Eve, Mentor Graphics, SpringSoft Inc, Breker Systems, Doulos, Jasper and Synopsys. And not least the participants, who made Verification Futures 2012 the event it has become, with a lot of lively debates and a number of frank views exchanged.

If you would like the chance to see some of these presentations, then click on the link below (the recordings will be available shortly): /verification-futures/

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Are you struggling to find time to learn about UVM? Too busy working on your current project?

UVM is now the defacto verification methodology for our industry. But how do you find the time to learn it given your current commitments?

Doulos, supplier of best in class training, is working with Test and Verification Solutions, a specialist verification company in India, to help you solve this problem. Why not spend an evening on 22nd November at DVClub learning the basics of UVM.

The goal of the evening is to enable engineers with experience in Verilog or VHDL to become productive in UVM by learning a small number of new coding idioms. It is free to attend with a free plate at the end of the evening when you will have a chance to network with fellow engineers. It is simple to register!

There are already over 150 registrations – so please register quickly before we fill up. Remote access is also available on the same page

Test and Verification Solutions is collaborating to bring Doulos training to India with public training classes in SystemC, TLM2.0, Comprehensive System Verilog and UVM.

  • Fundamentals of System C in Bangalore on November 20, 21, 22 System C
  • System C Modelling using TLM 2.0 in Bangalore on December 3,4,5
  • Comprehensive System Verilog in Bangalore on January 21, 22, 23, 24, 25
  • UVM Adopter Class in Bangalore on January 28, 29, 30

Contact Vandhana by email or 9841334752 for details of the above

Please note that we will be announcing more flexible ways of attending our courses at the DVClub as well as giving discounts for our courses to DVClub attendees. We look forwarding to seeing you on 22nd November in Bangalore!