Tag Archives: Verification Futures

NMI – Your Champion for the UK Electronics Systems Industry

T&VS organized a Verification Futures Conference on 4 Feb 2016 with a focus on “Challenges faced in Hardware Verification”.

Pete Davy, Director for FPGA Network at NMI, recently spoke in the Verification Futures conference on why NMI is the champion for the UK Electronics Systems Industry.

Find out the Presentation Slides and Recordings here

Fault analysis – What is Your Real FIT Size?

Accurately measuring a component’s Failures In Time (FIT) is the key to keep designs as simple as they should be, and avoiding over-design and schedule risks.

Avidan Efody, Verification Architect at Mentor Graphics, presented on the fault de-rating techniques available at various abstraction levels, and explained how they should all be combined to get a realistic estimate of FIT(Failures in Time) numbers and ISO 26262 architectural metrics at the Verification Futures Conference-“Challenges faced in Hardware Verification” on 4 Feb 2016.

You can view the slides and recordings here