Verification is the most critically important part of SRAM compiler development. Delivering low power SRAM solutions further exacerbates the challenges as near-threshold operation compounds multiple issues and increases the effects of process variation. This article highlights some of the methodologies and tools that meet the challenges in a robust, practical, and timely manner.
Learn more about how T&VS Verification IP Services help to address the burgeoning challenges of SRAM Verification.
Advancement in memory technologies and the demand for faster and higher density configuration leaves verification engineers in a limbo. This article from Synopsys describes how the memory world is debating the next wave of memory protocols and technologies such as next generation DDR, HBM, and NVDIMM.
Find out how T&VS helps customer in addressing next generation memory verification Challenges.
This article from Semiengineering captures the conversation between Cadence, Breker and Mentor Graphics on the advances in system-level verification and outlines how portable stimulus tackles the challenges of coverage and automotive reliability.
Find out how T&VS address the challenges of system-level verification methodologies.
This article from Cadence describes how the verification methodologies have been growing faster through the ages from Verification 0.0 to Verification 3.0. Additionally, this article also describes why security and functional safety will become a major area requiring verification in future.
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Kanagawa, Japan, 4 March 2016-Test and Verification Solutions(T&VS), a leader in software test and hardware verification solutions, today announced that it is opening a new office in Kanagawa, Japan.Underscoring a long-term commitment to service its local customers and partners, T&VS provides near shore presence inquality legal representation and dedicated to maintaining & expanding its capabilities / expertise across a wide range of practice areas to address the diverse needs of its clients.
Japan represents a promising market for T&VS products and services in both software testing and hardware verification, so opening a Japan office is a natural step in the continuing T&VS expansion story.We havestrong footprints in India, Singapore and Korea serving many tier-1 semiconductor and embedded companies.Our commitment to excellence, combined with our mission to deliver outstanding client service has earned the excellent reputation.
Since 2008, T&VS has been expanding its products and services, number of employees and its geographical footprint. T&VS now employs over 200 technical staff globally serving over 25 clients and partners including eight of the top ten global semiconductor companies as well as a number of highly motivated start-up companies.
Further information on T&VS products and services is available at www.testandverification.com
Stimulus generation is an important aspect of verification for creating both simple and the complex scenarios used to hit functional bugs in a design. This article from Tech Design outlines how to leverage a simple, standardized approach to describe generic and reusable stimulus sequences for verification IP.
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The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs.
Quality is even more critical for highly configurable types of IP. This article from EDN describes seven levels of IP verification to obtain sufficient quality throughout the entire SoC life cycle.
This article from Mentor Graphics lists and describes VIP master APIs that could be reused to generate stimulus on a cache coherent interface without worrying about accessing the cache model and other testbench objects that are typically needed to know about transaction attributes.
Instruction level read/ write and coherency APIs make it easy to write stimulus sequences on a cache coherent interface such as ARM® AMBA® 4 ACE and AMBA® 5 CHI.
Brandt Braswell, Member of the Technical Staff at Freescale Semiconductor describes how to mitigate some of the risk to make designs a first pass success. This blog outlines the solutions of two problems?
- What if scenarios to allow for variations in the circuits not planned?
- Does the design team have access to correlation data of the simulations models used for development against silicon data?
To measure the coverage of the validation test suite for the automotive products, the memory map coverage approach wasn’t adequate.
This article from Cadence outlines how to improve the validation test suite with system level coverage driven verification by using the native coverage support of the Palladium XP platform that scores a different types of coverage directly in its hardware.