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Project Verification Planning for Analog Designs

Successful projects leverage the investment in comprehensive methodology and resource planning, covering design and analysis flows that planning effort is especially important for functional verification. This article explains how to effectively plan functional verification for analog designs. Read More Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, [...]

2019-02-28T06:54:42+00:0028th February, 2019|Blog, Thought Leadership|

Efficient Hierarchical Verification for Low Power Designs

Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. This article discusses about how a new low power verification flow offers better runtime performance and reduced memory consumption without compromising QoR. Read More Find out how T&VS Verification services help to meet the challenging [...]

2019-01-29T10:16:17+00:0029th January, 2019|Blog, Thought Leadership|

Making IP Friendlier

Most standard protocol and interface IP enable verification engineers to check basic features, such as system start-up. VIP enables more detailed exploration. This is becoming increasingly important because of the growth in complexity of system-on-chip (SoC) designs. This article shows how to make IP more user friendly. Read More Find out how T&VS have developed a unique process that [...]

2019-01-11T05:52:21+00:0011th January, 2019|Blog, Thought Leadership|

Debug Tops Verification Tasks

Verification engineers are spending an increased percentage of their time in debug. There are a variety of reasons for this, including the fact that some SoCsare composed of hundreds of internally developed and externally purchased IP blocks and subsystems. This article outlines how engineers can overcome the problems in debugging and spend more time on other [...]

2019-01-07T06:27:48+00:007th January, 2019|Blog, Thought Leadership|

A New Approach to Low-Power Verification: Power Aware Apps

The effective verification of low-power designs has been a challenge for many years now.One of the main challenges for low-power verification engineers has been the fact that there is a disconnect between the traditional RTL and low-power objects. This article shows how to conduct effective verification for low-power designs. Read More Find out how T&VS Verification [...]

2018-12-20T10:12:01+00:0020th December, 2018|Blog, Thought Leadership|

FPGA Verification Challenges and Opportunities

The most disturbing finding from this year’s study relates to the number of FPGA projects with non-trivial bug escapes into production. An interesting correlation has been found between the improvement of reduced functional flaws contributing to non-trivial bug escapes and the maturing of FPGA projects’ functional verification processes. This article shows what are the latest [...]

2018-12-13T11:30:48+00:0013th December, 2018|Blog, Thought Leadership|

Mitigating Risk Through Verification

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. This article discusses about how automatic coverage model generation technology continues to advance. Read More Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify [...]

2018-12-11T08:30:12+00:0011th December, 2018|Blog, Thought Leadership|

Adding system-level, post-layout electrical analysis to HDAP design and verification

High-density advanced packaging (HDAP) offerings from both OSAT companies and traditional IC foundries are increasing in number and expanding in design options every day.Adoption of HDAP needs tools and supports to build designers’ confidence in the emerging technology. This article shows how to add system-level and post-layout electrical analysis to HDAP design and verification. Read [...]

2018-11-29T05:49:42+00:0029th November, 2018|Blog, Thought Leadership|

Advanced Process Nodes Make Emulation Essential

New process nodes with smaller features enable more transistors on a chip. Verification tools of all types including emulation have required constant upgrades to keep up with the capacity needed to test out the most advanced chips. This article shows how important is emulation for making advanced process nodes. Read More Find out how T&VS [...]

2018-11-14T05:29:28+00:0014th November, 2018|Blog, Thought Leadership|

Portable Stimulus enables new design and verification methodologies

Verification 3.0 is a profound change that will sweep through the semiconductor industry, changing tools, flows and methodologies almost everywhere it touches. When portable stimulus is applied to the verification tool, it is the start of a fundamental change in semiconductor development. This article explains how portable stimulus helps to develop new design and verification [...]

2018-10-31T08:02:17+00:0031st October, 2018|Blog, Thought Leadership|