Tag Archives: VerificationIP

T&VS releases one of the first C-PHY VIP solutions in the market

T&VS releases one of the first C- PHY  UVM VIP which has extensive constrained random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance to MIPI standard for C-PHY specification 1.0.

Pre-defined coverage bins enable easier extension and coverage collection. The VIP has been verified for protocol compliance with asureSign-T&VS’ in-house Requirements tracking tool.

For information, please visit here or contact us at [email protected]

July DVClub – An Efficient Methodology to Find Bugs with ABV

The next DVClub will be taking place on Monday, 7th July with locations in Bristol, Cambridge, Eindhoven, Grenoble, Sophia Antipolis and by Remote Access.  Laurent Arditi a Principal Engineer at ARM France will be joining the Sophia Antipolis venue to talk about ‘An Efficient Methodology to Find Bugs with ABV (Assertion Based Verification)’.

This presentation will cover how ABV is an important part of functional verification and will demonstrate how they have successfully applied ABV on different generations and classes of ARM microprocessor designs and will help managers and engineers understand how to apply ABV for good results by showing examples on recent CPUs developed by ARM to illustrate, and to “prove” ABV has a high RoI.

To find out more about Laurent and the other speakers visit the T&VS website and register for your place on the July DVClub.

Join OneSpin Solutions and Synopsys for Formal Verification

Join us on Thursday, 15th May 2014 for the annual Formal Verification Conference in Reading where you will be able to listen to Sergio Marchese a Senior Field Application Engineer with OneSpin Solutions.  He will be talking about Safety Critical Component Verification Leveraging Formal Techniques and how the use of formal techniques to apply elements of the standards during the verification of these safety critical components.

We will also be joined by Dan Benua, Principal Engineer at Synopsys who will be presenting Leveraging Formal in an Integrated Verification Platform which will explore some of the challenges and opportunities of combining formal technologies and methodologies with other verification techniques.

For more information about the speakers and to register to attend in person or by Remote Access, visit our website.

Verification Qualification DVClub Slides now Available

The April DVClub on Verification Qualification was another successful event with talks from Synopsys, Infineon, OneSpin Solutions, Dialog Semiconductors and Cray Ltd.  If you were unable to attend, or if you did and would like to review the slides, they are now available on the TVS website without having to log in, after 5th May you will have to be registered on the website to view the slides or recordings.

The next DVClub will be discussing Assertion Based Verification and will be taking place on Monday, 7th July 2014 why not register your interest and be one of the first to secure your place!

Do you have a story to tell that is relevant to Assertion Based Verification and would like to share it at the next DVClub? We are always looking for good end user case studies to share with the community.  Contact Mike Bartley for more information on how you can be a part of the next DVClub.

We look forward to seeing you at the next event!!!

T&VS launches larger library of Verification IP

Test and Verification Solutions (T&VS) has announced that it has expanded its asureVIP™ library of verification IP to cover protocols in MIPI, Memories, Universal Serial IO and Communication as well as a bespoke VIP development service.

The T&VS VIP offers many advantages to the user such as access to the source code, flexible licensing agreements and protocol compliance test suites. The latter enables the engineer to more quickly demonstrate that their design complies with the standard. The tests are mapped to the protocol specification so that the user can quickly see the intention of the test. Additionally the asureVIP™ library contains traffic generators which allows the chip integrator to quickly generate traffic across the interface. Synthesisable drivers and C interfaces allow the VIP to be used in emulation using SCEMI.

The UVM compliant asureVIP™ is written in native System Verilog so that debug becomes much easier given that the user has access to the code. Mike Bartley, Chief Executive Officer, Test and Verification Solutions said, “We have been working with clients on our VIP for some time now and a lot of the VIP is proven in a number of different environments and in silicon. Research suggests that companies are expanding their use of external VIP and adoption of UVM so I expect our UVM-compliant VIP to be very popular.”

The asureVIP™ library also contains eRM compliant VIP and in addition T&VS is able to VIP on demand under flexible ownership arrangements. The T&VS agile development process also means that the VIP is delivered in a number of short “sprints” allowing the client to make an early start on their verification.

For full details of the protocols available in the asureVIP™ library then please go our VIP page.

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TVS Delivers OVM Verification IP to Dialog Semiconductor

TVS’s expertise in the Open Verification Methodology (OVM) and verification IP development meant the company was able to deliver verification IP that Dialog could own long-term and reuse for future chip designs.

When Dialog, a fabless semiconductor company that creates energy-efficient mixed-signal integrated circuits optimised for personal mobile and automotive applications, decided to adopt OVM, they needed to upgrade their verification IP to be OVM compliant. The company chose TVS to supply that verification IP.

Dialog’s own verification staff were able to create the verification IP themselves but Dialog decided that buying the independent IP from TVS provided a number of significant advantages.

“As part of our advanced verification program, based around OVM, we needed certain verification IP that was OVM compliant” said Stuart Levine, Director of Engineering, Digital Methodology and IP at Dialog. “The TVS company-wide license allowed us to use the verification IP long-term without any license restrictions on how many simulations we could run in parallel.”

The TVS technical staff were able to provide the support that Dialog required to start using the verification IP immediately. TVS not only provides the source code but tests too which can be used in the customer IP and SoC verification.

“TVS were very flexible and provided us with good support,” commented Levine

The TVS staff have worked on numerous IP and SoC verification projects and thus understand the necessity of measuring progress through metrics. Combining this with their extensive knowledge of both OVM and the protocol allows them to deliver VIP that supports the metrics used by their customers.

“The Metric Driven Coverage capability built into the TVS VIP helps our customers to determine the actual protocol coverage. This helps their verification sign-off process enabling them to reduce time to market” added Mike Bartley, CEO of TVS.

Based on input from customers, TVS is also in the process of porting their VIP to be UVM compliant.

About TVS

TVS (Bristol, UK) delivers an independent testing service that not only reduces costs and time-to-market, but also improves product quality. TVS combines skills and experience in software testing, hardware verification and outsourcing to provide customers with an efficient, well-managed, quality assurance service. The company provides both consultancy and execution services using experienced engineering resources in several locations around the world.

www.tandvsolns.co.uk