NVMe VIP: Verification Features

Synopsys VC VIP for Non-Volatile Memory Express (NVMe) is designed to help thoroughly verify NVMe designs using both random and directed simulation. This article from Synopys describes verification features for NVMe and PCIe. Read More Learn more about T&VS VIP

2016-01-29T07:19:52+00:00 29th January, 2016|Blog, Thought Leadership|

Choosing the right VIP

VIP is used to determine if a design, or unit of a design, conforms to its specification.Selecting the right VIP demands a detailed evaluation process along with a comprehensive checklist. This article from Chip Design outlines how to choose the right VIP that it can support multiple methodologies, simulators and formal verification engines. Read More Learn more about [...]

2016-01-19T05:29:36+00:00 19th January, 2016|Blog, Thought Leadership|

NVMe VIP Architecture: Host Features

NVM Express or the Non-Volatile Memory Host Controller Interface is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. Synopsys VIP for NVMe is designed to help thoroughly verify NVMe designs using both random and directed simulation. This article from Synopsys outlines the NVMe commands by considering the [...]

2015-12-23T10:36:40+00:00 23rd December, 2015|Blog, Thought Leadership|

Verification IP for ARM AMBA 5 AHB5

This article from Cadence announced verification IP (VIP) for the ARM® AMBA® 5 Advanced High-Performance Bus 5 (AHB5) specifications. The simulation VIP, available now, supports all of the major logic simulators and enables verification engineers to perform in-depth verification with SystemVerilog-UVM testbenches. Read More

2016-07-08T07:04:56+00:00 7th December, 2015|Blog, Thought Leadership|

No to Know VIP – Part 3

If you have a UVM based testbench with one or multiple VIPs, your testbench could be more complex than your DUT and debugging this environment could be a major challenge. This article from Mentor Graphics outlines various built-in features of UVM VIP which helps your debug. Read More

2015-11-25T06:10:05+00:00 25th November, 2015|Blog, Thought Leadership|

How to cut Verification time with VIP

Verification IP (VIP) addresses many of the inherent challenges in verifying today’s complex designs, but must meet certain requirements. It needs to be proven, provide checks that ensure protocol compliance, and enable the collection and analysis of coverage data, minimizing the time to productive verification. This article from Mentor Graphics shows practical ways to use [...]

2015-11-12T06:10:57+00:00 12th November, 2015|Blog, Thought Leadership|

Resolving the limitations of a Traditional VIP for PHY Verification

Because of the complexities involved in the entire design verification flow, a traditional Verification IP tends to overlook the subtle aspects of the physical layer (PHY) verification, often leading to costly debug phases in the verification cycle. This article from Mentor Graphics describes the limitations of a traditional VIP, which can typically be resolved using [...]

2015-11-03T10:10:26+00:00 3rd November, 2015|Blog, Thought Leadership|

No to Know VIP – Part 2

VIP’s include various sequences API for rapid test creation like configure and as well as various scenario and error injection sequences. This article from Mentor Graphics outlines the QVIP Configuration and Sequences that allows users to become productive much earlier for application specific verification. Read More

2015-11-02T06:06:31+00:00 2nd November, 2015|Blog, Thought Leadership|

How do you choose the right memory VIP for your application?

This article from Tech Design Forum outlines how the Verification IP (VIP) can help, especially for memory implementations, providing tools that enable verification engineers to test an implementation against specific vendor memory components. Additionally this article also describes the key points, which help to choose the right memory VIP for your application. Read More

2015-10-30T06:07:38+00:00 30th October, 2015|Blog, Thought Leadership|

Benefits of native UVM VIP

Srinivasan Venkataramanan, Chief Editor at Verifnews.org, outlines “how to develop a set of base classes and API to create truly interoperable VIP?”   And also describes the advantages of native UVM as opposed to “disguised” ones. Read more

2015-12-03T05:52:17+00:00 7th August, 2015|Blog, Thought Leadership|
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