A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs

A RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration.A RISC-V microprocessor can be configured in several architectural modes depending upon the target market and applications. Further, each microprocessor implementation can have different micro-architectural parameters depending upon performance, and power considerations. Arun Chandra & Dr. Mike Bartley from T&VS outlines a hierarchical and configurable verification strategy for RISC-V based IP and SoCs.

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To help you deliver successful RISC-V based designs T&VS offer specific services that build on and extend the world-class test and verification services that we have been delivering to the semiconductor industry.

2018-03-13T07:24:16+00:0013th March, 2018|Blog, Thought Leadership|