Accelerating the Next Big Shift in Verification

This article from Cadence outlines the changes in verification methodology to accelerate the standardization process and describes the need for simulation less Integration, modes and register map verification, inferring and generating testbenches catering to multiple configurations of SoCs from IP and SoC Metadata.

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2015-09-29T05:39:23+00:0029th September, 2015|Blog, Thought Leadership|