An evaluation of the advantages of moving from a VHDL to a UVM testbench

VHDL was the language of choice for both RTL design and testbench, but there was no standardization or robustness for testbenches. UVM supports an industry standard, so it will encourage testbench standardization and also improves reusability through object oriented programming (OOP) features. This article from Mentor Graphics describes pros and cons of moving from a VHDL to a UVM testbench.

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