Are you testing your test in Formal Property Verification?

Coverage is a necessary but not sufficient metric to determine whether SoC verification is complete. It determines whether there is untested logic in the design, but doesn’t determine whether bugs will be found by the test environment. To get rid of this weakness in many verification strategies, it is also important to test your test.

This article from Tech Design Forum outlines how can you be sure that your formal testbench (assertions) test your entire design, find all the bugs and so shorten the time to tape out by using a thorough automated bug insertion (mutation) methodology.

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