Automation and Reuse in RISC-V Verification Flow

The Open RISC-V Instruction Set Architecture (ISA) backed by an ever-increasing number of the who’s who in the semiconductor and systems world, provides an alternative to legacy proprietary ISA’s.

This article from Mentor Graphics explores how automation in generating RTL, UVM verification environments, reference models and tests (programs) can rapidly improve productivity in the development of RISC-V cores.

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To help you deliver successful RISC-V based designs T&VS can offer specific services that build on and extend the world-class test and verification services that we have been delivering to the semiconductor industry

2017-07-26T05:48:50+00:00 26th July, 2017|Blog, Thought Leadership|
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