Breaking Down Power Management Verification

This blog from Mentor Graphics  describes the stages to create a scalable, progressive flow that allows users to begin the system-level low power verification early in the design and verification flow, using high-level models, adding detail and accuracy as the design matures. The stage which is used depends on how far along the design and its corresponding UPF description is in overall development.

The successive refinement at each stage allows users to break down a complex problem into smaller, targeted verification jobs and establish a feedback loop to and from the backend team.

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2015-07-16T05:16:07+00:0016th July, 2015|Blog, Thought Leadership|