Clock Domain Crossing in FPGA

Clock Domain Crossing (CDC) is a common occurrence in a multiple clock design. In the FPGA space, the number of interacting asynchronous clock domains has increased dramatically. It is normal to have not hundreds, but over a thousand clock domains. This article from Semiwiki highlights why CDC is a lingering issue, what its impact and the available remedy guidelines to ensure a robust FPGA design.

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2018-03-21T03:30:13+00:0021st March, 2018|Blog, Thought Leadership|