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DDR Simulation strategy catches bugs early

This article from EDN helps to identify the hidden design issues earlier in the design phase of the SoC and outlines how GLS (Gate Level Simulation) helps in visualizing design issues which can’t be predicted at the RTL level and thus helps in fixing them before silicon.

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2015-08-07T06:13:04+00:007th August, 2015|Blog, Thought Leadership|