Don’t over-constrain in formal property verification (FPV) flows

Formal property verification (FPV) is increasingly being used to complement simulation for system-on-chip (SoC) verification. FPV uses properties, i.e., assertions and constraints. Assertions are used in simulation as well, but the roles of constraints are different. This article from EDN describes why constraints are necessary for successful use of FPV.

Read More


Learn more about T&VS Formal Verification