Enabling FPGA prototyping of large ASIC and SoC designs

Prototyping large ASIC or SoC designs on a set of FPGAs presents a number of complex engineering challenges. However, those challenges are being met by the introduction of techniques such as multi-processing, automated partitioning with TDM, system chaining strategies and multi-FPGA debug schemes in commercial tools such as those provided by Synopsys.

The result is that it is increasingly possible to prototype designs of tens or even hundreds of millions of gates, accelerating debug and system software development.

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