Exploiting the power of reset in formal verification

The reset state of a module or SoC that is being verified can have a huge impact on the scope and correctness of the verification. When using simulation for verification, the reset phase is usually not a large concern. However, when using FPV, the reset state of the design is much more important and can be a powerful ally in your verification strategy. This article from Tech design describes how to utilize the power of reset in formal property verification.

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2016-03-11T07:04:04+00:0011th March, 2016|Blog, Thought Leadership|