Extending UVM Verification Models for the Analysis of Fault Injection Simulations

In high-reliability and safety-critical applications, RT and gate-level fault-injection simulations are often performed in order to ensure a certain level of fault detection coverage which is necessary to ensure compliance with standards such as ISO 26262.

This article from Mentor Graphics outlines the architecture of a fault injection platform and how this architecture can be easily integrated into a general purpose design verification environment (DVE) that is implemented using UVM.

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Find out how T&VS help verification engineers to ensure that the design has been successfully tested and verified.

2016-12-08T03:34:28+00:008th December, 2016|Blog, Thought Leadership|