Extending UVM Verification Models for the Analysis of Fault Injection Simulations

In high-reliability and safety-critical applications,RT and gate-level fault-injection simulations are often performed in order to ensure a certain level of fault detection coverage which is necessary to ensure compliance with standards such as ISO26262.

This article from Mentor Graphics describes the architecture for a complete fault injection platform and outlines how this architecture can be easily integrated into a general purpose design verification environment (DVE) that is implemented using UVM. Read More


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2016-06-22T06:33:04+00:0022nd June, 2016|Blog, Thought Leadership|