Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes. Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. As learnt in the ASIC domain, as designers’ ability to push more logic into a single chip grows, the verification of the functionality, timing and related aspects start exploding.
Just like the way the HDL synthesis requires specific tweaksforASIC vs. FPGA, the verification also requires tweaks and solutions to target FPGA verification. This has been the focus of Blue Pearl Software Inc (BPS)