FPGAs really DO get verified, but is it enough?

Doug Amos, FPGA Network Manager, NMI

DougAmos

I didn’t think it’s possible, but there are still those who believe that FPGA users do not perform verification; in fact I met a couple recently at an NMI FPGA Network event. To be fair, I also met there an FPGA user who actually DID go straight from Timing Analyser to download, only back-tracking to the Simulator when really necessary for debug. I remember doing the same myself, back in my early days as a “PIP-pilot” (those of a similar vintage will know what I mean).

Those days are long gone, except maybe for home-bench hobbyists, or others with time to kill. LOTS of time to kill.

Serious FPGA Users read on.

Of course, FPGAs lend themselves to so-called “Agile” design, and if verification is incomplete then the FPGA user is blessed with being able to ferret out bugs in system (without the boss finding out). However, the complexity and scale of FPGA designs easily matches that of many chip designs, and require EXACTLY the same diligence in RTL verification. But why is insufficient verification a problem?

Insufficient verification of an ASIC/SoC chip design is usually catastrophic but its impact on a project using FPGA may be no less so. Think about it. One of the prime reasons to use FPGA is time-to-market but if that time is squandered in the lab catching bugs that could have been trapped much more quickly during verification, then the boss still won’t be happy.

In-lab debug is a great feature of FPGA, but it is not a substitute for professional verification, and the newsflash (for some, it still seems) is that most FPGA designers in the country already understand this very well, as is shown from NMI’s recent survey.

Throughout October 2014, NMI ran a major survey of the usage of FPGAs in the UK and Ireland, in conjunction with New Electronics and with the help of leading partners in the FPGA Industry, including Aldec, Altera, FirstEDA, Mentor Graphics, Avnet-Silica, Synopsys and Xilinx. The survey covered a broad set of themes including application, skills and of course . . . verification.

At Verification Futures 2015 in Reading on Feb 5th, I will kick off the FPGA track by sharing some of NMI’s findings from the verification part of the survey. As a foretaste, I wonder what you think of this small datapoint exposed by the chart below. This chart shows that in their most recent FPGA projects, teams ALREADY spend significantly more time on verification than on in-lab debug.

FPGA_per_time

The questions we should consider during Verification Futures 2015 FPGA track are . . . Is this enough? Are FPGA users relying on the RTL designers own directed tests, or are they moving and into more efficient techniques e.g. assertions, functional coverage? Is there already a place for formal methods? Could in-lab debug become a more predictable exercise; perhaps based on re-use of verification test and results?

Verification Futures 2015 is the first forum outside of the NMI Members’ own FPGA Network where these results from the NMI FPGA Usage Survey results will show the current answers to these and other FPGA-related questions. I look forward to being part of the debate and I hope all you serious FPGA Users will make it along.

Register here for Verification Futures 2015

2018-02-23T12:02:57+00:00 22nd January, 2015|Blog, Thought Leadership|
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