Functional Verification Closure- Are we done yet?

Functional verification is the task of verifying that the logic design conforms to specification. It can be and is imprecise—how many tests we need, how much functional coverage is necessary for a high-quality design, how do we know we have a comprehensive verification plan, how many assertions should be implemented, and many more. This article from Cadence describes why functional verification can only be addressed by a well-defined and prescribed methodology.

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