Future challenges in design verification and creation

Today, Chip designers are using many techniques to verify a design and also using many EDA tools to address the functionality of the design, both at the logical and the physical level. But, especially with the growing introduction of the Internet of Things (IoT) devices and applications, the issues of verifying the safety and security are becoming a major concern. This article from Chip Design describes why security and functional safety will become a major area requiring verification in future.

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Find out how T&VS asureSIGN helps to address the challenges in design verification and creation.

2016-04-12T06:34:43+00:0012th April, 2016|Blog, Thought Leadership|