Graph-Based IP Verification in an ARM SoC Environment

This article provides a method for functional verification of an IP in a reusable environment. This allows for a low cost method for a verification engineer to re-verify an IP after it has been integrated into anSoC. Existing, tested, verification components are used to check that the IP is operating correctly within the target SoC environment.

In an SoC environment that contains multiple independent IP blocks, this approach can be extended to run multiple IP verification suites in parallel, providing a simple system level exerciser. By adding a top-level stimulus graph for coordination, a more complex SoC level verification environment can be constructed from the block-level components.

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2015-07-29T06:45:45+00:0029th July, 2015|Blog, Thought Leadership|