How a Cache Controller and Generic APIs Can Make It Easier to Generate Stimulus

This article from Mentor Graphics lists and describes VIP master APIs that could be reused to generate stimulus on a cache coherent interface without worrying about accessing the cache model and other testbench objects that are typically needed to know about transaction attributes.

Instruction level read/ write and coherency APIs make it easy to write stimulus sequences on a cache coherent interface such as ARM® AMBA® 4 ACE and AMBA® 5 CHI.

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