How Formal Verification saves time in digital IP design

It is well known that the task of verification looms large in the design of digital IP, as well as the design of SoCs. The target is to reach 100% for both RTL code and functional coverage, minimizing the time spent obtaining it.

This article from EDN describes a different approach for digital IP verification based on formal methodology, exhaustively verifying the functionalities through the definition of properties. This new flow has been used during the design of a digital IP and has proven to significantly shrink verification time.

Read More