How to expose X-optimism issues in ASIC and FPGA design

X-optimism occurs when an unknown X value is incorrectly resolved to a known value in RTL simulation. Optimism is difficult to detect and debug because the X is no longer visible once the optimism occurs. This article from Tech Design describes how Real Intent’s Ascent XV uses static analysis to identify potential X-optimism issues at RTL so they can be fixed before simulation, ensuring efficient and accurate runs.

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Find how T&VS solve X-optimism issues in ASIC and FPGA design

2016-03-10T05:19:08+00:0010th March, 2016|Blog, Thought Leadership|