A DFT App enables execution of complete pattern sets for DFT verification in a reasonable time to shorten the pattern development cycle. Scalable hardware and a compiler enables test pattern validation for large gate-level designs with scan and other test structures embedded into the design. The DFT App is interoperable with other tools by supporting standard STIL format file. Verification Consultant, Lauro Rizzatti, describes how hardware emulation provides enough verification power to move DFT into the chip design thus accelerating the time to market, improves performance, increasing the yield, and ultimately augmenting profits.
Find out more about how T&VS adds Design for Testability to services portfolio, enabling customers to reduce time to market.