Increase Verification Productivity with Questa® UVM Debug

verification-horizons-tom-fitzpatrick-editor
In a recent article published in the November edition of Mentor Graphics’ Verification Horizons, Dr. Mike Bartley, founder and CEO, Suresh Babu, Solutions Architect, and Shyam Ramaswamy, Sales and Business Development Manager, TVS, have shared their experience of using Questa® UVM debug .
A short abstract of the article is enclosed below. To read the full article visit Verification Horizons.

Debug is one of the major bottlenecks that verification teams face today. Traditionally, to make the debug task easier, significant effort is invested upfront by following standard coding guidelines and writing code that is debug friendly. The near-universal adoption of UVM has, while making the verification process a lot more streamlined, however, increased the debug challenge.

Questa UVM debug helped the TVS team channelize effort that was otherwise being unproductively spent in fixing verification environment issues towards more critical verification tasks like feature addition and coverage closure. Using Questa UVM debug, TVS was able to reduce debug times on the ARM® VIP development activity by as much as 35% .

Read the full article at Verification Horizons.

2014-11-27T13:10:26+00:00 27th November, 2014|Blog, Thought Leadership|
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