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Leveraging HLS/HLV flow for ASIC Design productivity

High-level Synthesis is an automated design process that lets hardware architects to build and verify hardware efficiently.  This article from SemiWiki describes how HLS/HLV methodology works efficiently at a higher level (C/C++/SystemC) and complements the RTL flow for ASIC design productivity.

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Learn more about T&VS SystemC model for the Advanced Memory Subsystem

2016-01-21T06:03:38+00:0021st January, 2016|Blog, Thought Leadership|