Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation.

This article from One Spin Solutions outlines how verification is performed on SystemC designs at the HDL level on the synthesized code and describes the use of formal verification within a high level synthesis design flow.

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2015-10-06T06:51:33+00:006th October, 2015|Blog, Thought Leadership|