Mentor builds Simulation-Emulation bridge to ‘Verification 3.0’

Data on EDA spending suggests that emulation is the fastest growing. The EDA Consortium data shows the sector growing from $188m in 2010 to $363m in 2012.

Mentor suggests that once designs pass 250 million gates then the gate counts and complexity combined justifies the investment based on ROI. Combined with the need for hardware-software co-verification then we can start to understand the reasons behind the increased demand.

Of course, one purchased then emulation needs to be integrated into the verification strategy to maximize the ROI. The new Mentor emulation operating system, Veloce OS3, will allow a much larger number of simulation tasks to be run in emulation. For example,

  • Veloce boxes will now support SystemVerilog functional coverage, assertion-based verification and testbenches, UPF for low-power verification and both UVM and C/C++ testbenches.
  • It enables greater reuse and speeds the simulation-to-emulation port for acceleration and software test.
  • The introduction of a Unified Coverage Database providing coverage data in a common format will give a more consistent view of overall progress. This will of course also mean that emulation results can now be imported into the TVS asureSIGN tool.
  • An integrated hardware debugger, Visualizer; an integrated software debugger, Codelink; verification IP common to both Questa and Veloce; and support for virtual peripherals to move emulators from the lab into data centers.

The drivers for increased use of emulation (gate counts, complexity and HW-SW co-verification) will of course not relent and so the future for emulation is bright. It is good to see innovations from vendors look to increase ROI.

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