New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog and UVM Environments

Cadence launched two new Verification IP RAKs, that demonstrate how you can improve your productivity and maximize the benefits of Cadence tools and technologies in the Verification IP space. The first RAK provides a basic back-to-back GMII VIP example in pure SystemVerilog with an application note and four labs. The second RAK one Integrating M-PCIe Verification IP for system Verilog user.

Read  more about these VIP Raks.