On-Chip Debug – Reducing Overall ASIC Development Schedule Risk

With ASIC complexity on the increase, many silicon design teams still face serious schedule risk from long post-silicon debug cycle and unplanned spins. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions. This article from Mentor Graphics outlines how on-chip logic analyzer solution allows verification teams to root-cause complex issues in a much shorter time.

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2015-11-23T05:59:29+00:0023rd November, 2015|Blog, Thought Leadership|