PA GLS: The Power Aware Gate-level Simulation

In post-synthesis, gate-level netlist (GL-netlist), power aware (PA) simulation, the fundamental focus is to identify PA specific cells already present in the netlist. The associated UPF with the netlist design, determines the supply network and power connectivity to these special PA cells, and aid to keep their outputs from being corrupted.

Hence, the GL-netlist-based power aware simulation input requirements are mostly the same as for RTL simulation. This article summarizes how the Questa® power aware simulation tool conducts power aware simulation on the GL-netlist similar to the RTL design.

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